14-07-2012, 12:17 PM
FPGA IMPLEMENTATION OF DIGITAL FILTERS
[attachment=27634]
INTRODUCTION
The most common approaches to the implementation of digital
filtering algorithms are general purpose digital signal processing
chips for audio applications, or special purpose digital filtering
chips and application-specific integrated circuits (ASICs)
for higher rates [9, 14]. This paper describes an approach to the
implementation of digital filter algorithms on field programmable
gate arrays (FPGAs).
Recent advances in FPGA technology have enabled these devices
to be applied to a variety of applications traditionally reserved
for ASICs. FPGAs are well suited to datapath designs,
such as those encountered in digital filtering applications. The
density of the new programmable devices is such that a nontrivial
number of arithmetic operations such as those encountered
in digital filtering may be implemented on a single device. The
advantages of the FPGA approach to digital filter implementation
include higher sampling rates than are available from traditional
DSP chips, lower costs than an ASIC for moderate volume
applications, and more flexibility than the alternate approaches.
In particular, multiple multiply-accumulate (MAC) units may be
implemented on a single FPGA, which provides comparable performance
to general-purpose architectures which have a single
MAC unit.
BACKGROUND
Research on digital filter implementation has concentrated on custom
implementation using various VLSI technologies. The architecture
of these filters has been largely determined by the target applications
of the particular implementations. Several widely used
digital signal processors such as the Texas Instruments TMS320,
Motorola 56000, and Analog Devices ADSP-2100 families have
been designed to efficiently implement filtering operations at audio
rates. These devices are extremely flexible, but are limited in
performance. High performance designs for filtering at sampling
rates above 100 MHz have also been demonstrated using CMOS
[3, 4, 6, 8, 9, 14, 17, 19, 20, 21] and BiCMOS [8, 20, 22] technologies,
using approaches ranging from full customto traditional
factory-configured gate arrays. These efforts have produced high
performance designs for specific application domains.
Implementation ofMultiplier
The combinatorialmultiplier uses one CLB per partial product bit.
A 2-inputAND gate generates each partial product, but additional
circuitry is required to add together all partial products of equal
weight. The total number of CLBs used for the multiplier in this
case is 64 and the basic cell structure is illustrated in Figure 2.
MAC Implementation
We use the most significant 8 output bits of the multiplier as the
input to the low order bits of the adder. The 8-bit input of the
adder is sign-extended and added with previous outputs using
two’s complement addition.
The basic structure of the MAC unit can use pipeline registers
between themultiplier and accumulator to increase the throughput.
The flip-flops in the CLBs are used as pipeline registers and hence
no additional CLBs are needed.
High Performance Filters on FPGAs
The inverted form shown in Figure 6© is well-suited for achieving
a high sampling rate even for higher order filters. This is
possible because the throughput does not depend strongly on the
number of taps due to extensive pipelining. The fact that the
multipliers occupy a large area, however,might render the implementation
of higher order filters impractical.
It has been shown in [2] that a high performance FIR filter
with substantial number of taps can be implemented on FPGAs
by approximating the filter coefficients to a sum or difference of
two power-of-two terms. Implementation of digital filters may
be simplified by using only a limited number of power-of-two
terms so that only a small number of shift and add operations is
required. A variety of techniques have been proposed [15, 16]
to minimize the deterioration of the frequency response due to
these constraints. Such coefficient optimization techniques yield
performance sufficient for most practical applications.
PIPELINEDMAC UNITS
It has been mentioned that the delay in the multiplier poses a
major limitation on the maximum sampling rate that can be attained.
Array multipliers can be configured to allow a pipelined
mode of operation, where the execution of separate multiplications
overlaps. If this mode of operation is applied, the long delay
associated with the carry propagating addition performed in the
last row of the array multiplier can be minimized, since it determines
the throughput of the pipeline. This approach has been
shown to yield extremely high speed customimplementations [5].
With this more aggressive pipelining, a MAC unit which operates
at rates approaching 100 MHz can be implemented on the
XC4000-series FPGAs, thus providing a building block for high
sampling rate filters. The pipelined MAC units can be applied to
high performance FIR and IIR filter structures, as well as other
signal processing algorithmswhich can tolerate the pipeline delay.
[attachment=27634]
INTRODUCTION
The most common approaches to the implementation of digital
filtering algorithms are general purpose digital signal processing
chips for audio applications, or special purpose digital filtering
chips and application-specific integrated circuits (ASICs)
for higher rates [9, 14]. This paper describes an approach to the
implementation of digital filter algorithms on field programmable
gate arrays (FPGAs).
Recent advances in FPGA technology have enabled these devices
to be applied to a variety of applications traditionally reserved
for ASICs. FPGAs are well suited to datapath designs,
such as those encountered in digital filtering applications. The
density of the new programmable devices is such that a nontrivial
number of arithmetic operations such as those encountered
in digital filtering may be implemented on a single device. The
advantages of the FPGA approach to digital filter implementation
include higher sampling rates than are available from traditional
DSP chips, lower costs than an ASIC for moderate volume
applications, and more flexibility than the alternate approaches.
In particular, multiple multiply-accumulate (MAC) units may be
implemented on a single FPGA, which provides comparable performance
to general-purpose architectures which have a single
MAC unit.
BACKGROUND
Research on digital filter implementation has concentrated on custom
implementation using various VLSI technologies. The architecture
of these filters has been largely determined by the target applications
of the particular implementations. Several widely used
digital signal processors such as the Texas Instruments TMS320,
Motorola 56000, and Analog Devices ADSP-2100 families have
been designed to efficiently implement filtering operations at audio
rates. These devices are extremely flexible, but are limited in
performance. High performance designs for filtering at sampling
rates above 100 MHz have also been demonstrated using CMOS
[3, 4, 6, 8, 9, 14, 17, 19, 20, 21] and BiCMOS [8, 20, 22] technologies,
using approaches ranging from full customto traditional
factory-configured gate arrays. These efforts have produced high
performance designs for specific application domains.
Implementation ofMultiplier
The combinatorialmultiplier uses one CLB per partial product bit.
A 2-inputAND gate generates each partial product, but additional
circuitry is required to add together all partial products of equal
weight. The total number of CLBs used for the multiplier in this
case is 64 and the basic cell structure is illustrated in Figure 2.
MAC Implementation
We use the most significant 8 output bits of the multiplier as the
input to the low order bits of the adder. The 8-bit input of the
adder is sign-extended and added with previous outputs using
two’s complement addition.
The basic structure of the MAC unit can use pipeline registers
between themultiplier and accumulator to increase the throughput.
The flip-flops in the CLBs are used as pipeline registers and hence
no additional CLBs are needed.
High Performance Filters on FPGAs
The inverted form shown in Figure 6© is well-suited for achieving
a high sampling rate even for higher order filters. This is
possible because the throughput does not depend strongly on the
number of taps due to extensive pipelining. The fact that the
multipliers occupy a large area, however,might render the implementation
of higher order filters impractical.
It has been shown in [2] that a high performance FIR filter
with substantial number of taps can be implemented on FPGAs
by approximating the filter coefficients to a sum or difference of
two power-of-two terms. Implementation of digital filters may
be simplified by using only a limited number of power-of-two
terms so that only a small number of shift and add operations is
required. A variety of techniques have been proposed [15, 16]
to minimize the deterioration of the frequency response due to
these constraints. Such coefficient optimization techniques yield
performance sufficient for most practical applications.
PIPELINEDMAC UNITS
It has been mentioned that the delay in the multiplier poses a
major limitation on the maximum sampling rate that can be attained.
Array multipliers can be configured to allow a pipelined
mode of operation, where the execution of separate multiplications
overlaps. If this mode of operation is applied, the long delay
associated with the carry propagating addition performed in the
last row of the array multiplier can be minimized, since it determines
the throughput of the pipeline. This approach has been
shown to yield extremely high speed customimplementations [5].
With this more aggressive pipelining, a MAC unit which operates
at rates approaching 100 MHz can be implemented on the
XC4000-series FPGAs, thus providing a building block for high
sampling rate filters. The pipelined MAC units can be applied to
high performance FIR and IIR filter structures, as well as other
signal processing algorithmswhich can tolerate the pipeline delay.