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Full Version: Open Core Platform based on OpenRISC Processor and DE2-70 Board
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Open Core Platform based on OpenRISC Processor and DE2-70 Board
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Introduction

This chapter intends to give an introduction and a chapter overview to the
master thesis made by Xiang Li and Lin Zuo.


The Design Reuse methodology with IP cores

As the increasing complexity of the digital electronic systems and the
growing time-to-market pressure, engineers are forced to utilize previously
made blocks, i.e. IP cores, as many as possible into new designs.
This is called design reuse methodology.
The methodology produces more and more IP cores that are ready
to use. These IP cores provide great convenience when designing new
systems. For example in this thesis project we can quickly build a
system with the selected IP cores. If we had to create those IP cores
ourselves, it would be an impossible work for us to finish the system
within limited time.

The appearance of the Open Core community

Most IP cores are implemented by Hardware Description Languages
(HDLs), either VHDL or Verilog HDL. The HDL source codes can be
further synthesized to digital circuits by software tools.
Similarly to the free software community, there has emerged an open
core community, where the designers publish their IP core HDL source
codes that are protected by open source licenses. The open source IP
cores are called in short Open Cores.
The OpenCores organization is the world’s largest site/community for
development/discussion of open source hardware IPs [2, 3]. In the website,
there are hundreds of opening or finished projects regarding to the
open cores, which cover from CPUs to all kinds of peripherals. Some of
the open cores are with very good quality and have been successfully
used in commercial/industrial projects.



Thesis Objectives

The thesis is to implement a computing platform with open cores. However
this is a very broad topic. After discussed and approved by the supervisors,
we had elaborated and refined the thesis into detailed tasks. In this section
the tasks of the thesis are summarized, including both we achieved and failed
due to the time limitation.
The original thesis announcement made by Johan J¨orgensen is copied as
Appendix A, from where we can get an overall idea of the initial purposes
of the thesis:
1. Evaluate quality, difficulty of use and the feasibility of open source IPs
2. Design the system in a FPGA and also evaluate the system performance
3. Investigate license issues and their impact on commercial use of open
source IP
4. Port embedded Linux to the system



Chapter Overview

The thesis contains 7 chapters. An overview of the chapters is given below.
As mentioned before, the contents of this thesis focuses mainly on the tasks
that Xiang Li was responsible. For Lin Zuo’s part, e.g. system performance
comparison, please refer to Lin’s thesis [6].
Chapter 1 is the chapter you are reading which gives an introduction to
the thesis.
Chapter 2 introduces 3 widely used open sources licenses: GPL, LGPL and
the BSD license, and discusses the impacts of the licenses for the open cores.
The chapter is placed before the system implementation chapters because
it is a primary task to investigate. We don’t want to violate the licenses
while using open cores. Also it would be interesting to know the influences
of the open sources licenses if an open core based system will be used for
commercial purposes.
From Chapter 3 to Chapter 6, the implementation of the open core based
computing platform is described.