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INTRODUCTION
Transistors are the microscopic, silicon-based switches that process the ones and zeros of the digital worlds and are the fundamental building block of all semiconductor chips. With traditional planar transistors, electronic signals travel as if on a flat, one-way road. This approach has served the semiconductor industry well since the 1960s. But, as transistors shrink to less than 30 nanometers (billionths of a meter), the increase in current leakage means that transistors require increasingly more power to function correctly, which generates unacceptable levels of heat.
Intel's tri-gate transistor employs a novel 3-D structure, like a raised, flat plateau with vertical sides, which allows electronic signals to be sent along the top of the transistor and along both vertical sidewalls as well. This effectively triples the area available for electrical signals to travel, like turning a one-lane road into a three-lane highway, but without taking up more space. Besides operating more efficiently at nanometer-sized geometries, the tri-gate transistor runs faster, delivering 20 percent more drive current than a planar design of comparable gate size.
The tri-gate structure is a promising approach for extending the TeraHertz transistor architecture Intel announced in December 2001. The tri-gate is built on an ultra-thin layer of fully depleted silicon for reduced current leakage. This allows the transistor to turn on and off faster, while dramatically reducing power consumption. It also incorporates a raised source and drain structure for low resistance, which allows the transistor to be driven with less power. The design is also compatible with the future introduction of a high K gate dielectric for even lower leakage.
Intel researchers have developed "tri-gate" transistor design. This is one of the major breakthroughs in the VLSI technology. The transistor is aimed at bringing down the transistor size in accordance with the Moore’s Law. The various problems transistors with very small size face have to be overcome. A reduction in power dissipation is another aim. This is to develop low power microprocessors and flash memories.
Tri-gate transistors show excellent DIBL, high sub threshold slope, high drive and much better short channel performance compared to CMOS bulk transistor. The drive current is almost increased by 30%. The thickness requirement of the Si layer is also relaxed by about 2-3 times that of a CMOS bulk transistor.
Tri- gate transistors are expected to replace the nanometer transistors in the Intel microprocessors by 2010. 60 nm tri-gate transistors are already fabricated and 40 nm tri-gate transistors are under fabrication. Tri-gate transistor is going to play an important role in decreasing the power requirements of the future processors. It will also help to increase the battery life of the mobile devices.
HISTORY
Since their inception in the late 1950s, planar transistors have acted as the basic building block of microprocessors. The scaling of planar transistors requires the scaling of gate oxides and source/drain junctions. In 2002 Intel developed the world™s first CMOS tri-gate transistor,which employs a novel three-dimensional gate design that improves the drive current. Tri- gatetransistors are expected to replace the nanometer transistors in the Intel microprocessors by 2010
TRI-GATE FABRICATION & DEVICE CHARACTERISTICS
Tri-Gate transistors down to 30nm were fabricated in the following manner. To get body widths of the same approx. size as the polysilicon gate, the body was first fabricated by treating it in a similar manner to polysilicon, using aggressive poly-silicon lithography and etch techniques to get body thicknesses equal to gate lengths. The body was then doped to obtain acceptable threshold voltages (Vt) using conventional boron implants.
No halo implants were used for setting Vt, nor were there any angled implants used anywhere in the process. This is in contrast to Double-Gate (DG), and this is possible since the Tri-Gate very much resembles bulk transistor from the processing point-of-view. However, to get the right Vt’s, it was found necessary to protect the Tri-Gate bodies from boron outdiffusion into the surrounding oxide by an N2O oxidation before gate definition. The gate stack included polysilicon gates, and a conventional physical oxide thickness of 15 Angstroms. Raised source/drains were used to reduce parasitic resistances and the transistor was silicided using nickel. CMOS Tri-Gate transistors were fabricated down to 30nm. The examples of CMOS devices at Lg=60nm. the cross-section of the nMOS device . This device has body dimensions of HSi=36nm and WSi=55nm, The NMOS device had a subthreshold slope (S/S) = 68 mV/decade, DIBL=41mV/V, Ion=1.14mA/mm and Ioff=70nA/mm at Vcc= 1.3V. The PMOS device showed S/S=69.5 mV/decade, DIBL= 48mV/V, Ion=520mA/mm and Ioff = 24nA/mm at Vcc=1.3V
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