21-07-2012, 04:40 PM
AN OVERVIEW OF ADVANCED ELECTRONIC PACKAGING TECHNOLOGY
[attachment=28405]
Overview of Microelectronic Packaging
Definition of Electronic Packaging
An electronic package is the portion of an electronic structure that protects an electronic/electrical element and its environment from each other. [1] Packaging is the bridge that interconnects the ICs and other components into a system-level board to form electronic products. An integration of many circuits or components on a single chip is defined as an integrated circuit (IC). ICs are classified by their material and composition, degree of integration, number of transistor elements, principles of operation, manufacturing method and device type. Table 1.1 indicates how ICs are classified by integration level.
Function of Electronic Packaging
IC packaging has three important parameters: [1] The amount of I/O which determines the pitch of the IC package as well as the wiring needs at the system level, the size of the IC which affects the reliability of the IC to package connection and the power which affects the heat dissipation properties of IC and system level packaging.
The functions of an IC package are to protect, power, and cool the microelectronic device and to provide an electrical and mechanical connection between the chip and the outside world. The package for an IC must provide a structure to physically support the chip, a physical housing to protect the chip from the environment, an adequate means of removing heat generated by the chip or system, electrical connections to allow signal and power access to and from the chip, and a wiring structure to provide an interconnection between the chips of an electronic system. These basic functions are illustrated in Fig. 1.4.
Driving Forces of Packaging Technology
Historically, packaging has always been a substantial fraction of the price of an IC (10 to 50%). Cost and performance are the primary concerns in electronic packaging. In general, packaging costs are driven by the materials and fabrication requirements associated with the actual manufacturing and by the testing and rework associated with manufacturability. In the case of multi-chip packaging, manufacturing costs affected by the reliability of the IC chips, generally referred to as known good die. Performance is a function of electrical, thermal, and mechanical design constraints, material selection, and fabrication limitations.
Electrical Packaging Design Process
Electrical package design is the process that defines the electrical signal and power paths through the package in a way that meets the overall system requirements. Ultimately, the end result of the design process is the geometrical layout of interconnects and the specification of materials and their geometries needed to meet the system requirements. The electrical design procedure of the package starts with the determination of the electrical specifications for the package. Basically, these specifications are based on the system and chip performance.
Recent Trends in Advanced Electronic Packaging
Traditional electronic packaging presents significant problems. The IC packaging which provides I/O connections from the chip to the rest of the system is typically bulky and costly, limiting both the performance and the reliability of the IC. In addition, system packaging that provides the interconnection of components on a circuit board is similarly bulky and costly and limits the electrical and mechanical performance. To address these concerns, current trends in electronic packaging technology fall into two categories; the high performance system packaging and mobile platform packaging.
Wafer-Level Chip Scale on Package (WL-CSP) Technology – Nokia 702
Wafer-level packaging (WLP) refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process assembling the package of each individual unit after wafer dicing. WLP is essentially a true chip-scale packaging (CSP) technology, since the package size is practically of the same as the die. Furthermore, wafer-level packaging can accomplish true integration of wafer fab, packaging, test, and burn-in at wafer level. Thus, the device manufacturing process can be streamlined ultimately using WLP technology.
[attachment=28405]
Overview of Microelectronic Packaging
Definition of Electronic Packaging
An electronic package is the portion of an electronic structure that protects an electronic/electrical element and its environment from each other. [1] Packaging is the bridge that interconnects the ICs and other components into a system-level board to form electronic products. An integration of many circuits or components on a single chip is defined as an integrated circuit (IC). ICs are classified by their material and composition, degree of integration, number of transistor elements, principles of operation, manufacturing method and device type. Table 1.1 indicates how ICs are classified by integration level.
Function of Electronic Packaging
IC packaging has three important parameters: [1] The amount of I/O which determines the pitch of the IC package as well as the wiring needs at the system level, the size of the IC which affects the reliability of the IC to package connection and the power which affects the heat dissipation properties of IC and system level packaging.
The functions of an IC package are to protect, power, and cool the microelectronic device and to provide an electrical and mechanical connection between the chip and the outside world. The package for an IC must provide a structure to physically support the chip, a physical housing to protect the chip from the environment, an adequate means of removing heat generated by the chip or system, electrical connections to allow signal and power access to and from the chip, and a wiring structure to provide an interconnection between the chips of an electronic system. These basic functions are illustrated in Fig. 1.4.
Driving Forces of Packaging Technology
Historically, packaging has always been a substantial fraction of the price of an IC (10 to 50%). Cost and performance are the primary concerns in electronic packaging. In general, packaging costs are driven by the materials and fabrication requirements associated with the actual manufacturing and by the testing and rework associated with manufacturability. In the case of multi-chip packaging, manufacturing costs affected by the reliability of the IC chips, generally referred to as known good die. Performance is a function of electrical, thermal, and mechanical design constraints, material selection, and fabrication limitations.
Electrical Packaging Design Process
Electrical package design is the process that defines the electrical signal and power paths through the package in a way that meets the overall system requirements. Ultimately, the end result of the design process is the geometrical layout of interconnects and the specification of materials and their geometries needed to meet the system requirements. The electrical design procedure of the package starts with the determination of the electrical specifications for the package. Basically, these specifications are based on the system and chip performance.
Recent Trends in Advanced Electronic Packaging
Traditional electronic packaging presents significant problems. The IC packaging which provides I/O connections from the chip to the rest of the system is typically bulky and costly, limiting both the performance and the reliability of the IC. In addition, system packaging that provides the interconnection of components on a circuit board is similarly bulky and costly and limits the electrical and mechanical performance. To address these concerns, current trends in electronic packaging technology fall into two categories; the high performance system packaging and mobile platform packaging.
Wafer-Level Chip Scale on Package (WL-CSP) Technology – Nokia 702
Wafer-level packaging (WLP) refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process assembling the package of each individual unit after wafer dicing. WLP is essentially a true chip-scale packaging (CSP) technology, since the package size is practically of the same as the die. Furthermore, wafer-level packaging can accomplish true integration of wafer fab, packaging, test, and burn-in at wafer level. Thus, the device manufacturing process can be streamlined ultimately using WLP technology.