23-07-2012, 02:19 PM
I/O System Design
[attachment=28506]
Overview of 8088 I/O System
65,536 possible I/O ports
Data transfer between ports and the processor is over data bus
8088 uses address bus A[15:0] to locate an I/O port
AL (or AX) is the processor register that takes input data (or provide output data)
Input Port Implementation
The outputs of the gating device are high impedance when the processor is not accessing the input port
When the processor is accessing the input port, the gating device transfers input data to CPU data bus
The decoding circuit controls when the gating device has high impedance output and when it transfers input data to data bus
Serial Data Transfer
Asynchronous v.s. Synchronous
Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication
Synchronous transfer does not transfer extra bits. However, it requires clock signal
[attachment=28506]
Overview of 8088 I/O System
65,536 possible I/O ports
Data transfer between ports and the processor is over data bus
8088 uses address bus A[15:0] to locate an I/O port
AL (or AX) is the processor register that takes input data (or provide output data)
Input Port Implementation
The outputs of the gating device are high impedance when the processor is not accessing the input port
When the processor is accessing the input port, the gating device transfers input data to CPU data bus
The decoding circuit controls when the gating device has high impedance output and when it transfers input data to data bus
Serial Data Transfer
Asynchronous v.s. Synchronous
Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication
Synchronous transfer does not transfer extra bits. However, it requires clock signal