24-07-2012, 11:18 AM
Process Integration Considerations for 300 mm TSV Manufacturing
[attachment=28616]
Abstract
Through-silicon via (TSV) will transition to high
volume production when end-customer value (as exhibited by
functionality, performance, form factor, etc.) are delivered at
equivalent yield and cost.While this has been successfully achieved
for CMOS image sensors (starting with 200 mm), significant work
remains to be done in the TSV value chain (design–materials–
process–packaging–test) in the communication and memory
segments. This paper will address key unit process/processintegration
challenges and highlight recent internal/ partner and
industry findings in the context of TSV manufacturability at
300 mm.
INTRODUCTION
THROUGH-SILICON VIA (TSV) is emerging as a viable
method of joining together stacked integrated circuits
(ICs). Using vertical electrical interconnects that pass through
the die, this approach can reduce interconnect lengths and
enable more compact form factors. These interconnects are
formed by etching vias through the silicon wafer, then filling
them with metal. The silicon die are then stacked and bonded
to each other using the deposited metal. The two TSV methods
commonly used today (but sometimes with different terminology)
involve “via-first/via-middle” and “via-last” process flows.
While the via-last approach appears to be the simpler flow,
with minimum impact to circuit layout, the via-first scheme
(although requiring more changes to interconnect circuit layout)
may ultimately offer the greatest benefits by enabling a
higher density of inputs/outputs (I/Os). This paper examines the
key TSV process technologies and discusses challenges in their
integration for production.
TSV INTEGRATION SCHEMES
In the via-first flow, TSVs are created from the device side
of a full thickness wafer during processing in a wafer fab.
Typically, the vias are 5–10 μm in diameter and 50–100 μm
deep with a nominal aspect ratio of ten. These are also called
iTSVs (interconnect TSVs) as they are made during highdensity
interconnect metallization. In certain instances when
the vias need to be filled with tungsten CVD (instead of the
more common copper), aspect ratios can be up to 20, but this
leads to its own challenges that are outlined later in this paper.
These vias are typically created in the middle of line (after
contact) or during the back-end of line interconnect formation.
Via middle TSVs offer the best flexibility in layout and design.
Interconnect wires fromM1 through Mx may be permitted
to go above them. The dielectric stack on top of the silicon is
also the thinnest at this point in the integration cycle, thereby
simplifying the etch process and minimizing any undercut that
may occur at the interface between the dielectric stack and
silicon. On the other hand, when vias are etched at the very
end of the line, the TSVs have to be etched through a thick
and complex dielectric stack prior to etching the silicon. While
this poses challenges in etching and other processes, it poses
even more challenges for design and layout. One would need to
ensure that the keep-out area around the TSV is maintained all
through the M1–Mx metal stacks, thereby placing unnecessary
constraints in chip layout.
VIA ETCH
Via etch is the first process in the sequence; it sets the foundation
for successful integration and, hence, is very important.
Deep silicon etch can be performed by two different modes of
operation: the Bosch [1] or time-multiplexed gas-modulation
(TMGM) process and the “steady-state” process.
In the Bosch process, the etch reactor alternates between
gases that etch the silicon and gases that deposit a protective
passivation coating on the newly etched feature using
polymerizing chemistries, such as C4F8. The process creates
a series of etched “scallops” in the silicon, which can vary
in size depending on process parameters. With advanced RF
modulation and gas switching techniques, the scallop can be
virtually eliminated.
BARRIER-SEED DEPOSITION, ECD VIA FILL, AND
CHEMICAL–MECHANICAL PLANARIZATION
The most common approach for forming a conductive pathway
through the etched via involves depositing a copper barrier/
seed layer followed by ECD copper fill. A CVD liner followed
by tungsten CVD fill has been demonstrated in a certain TSV
work [3]. However, tungsten CVD deposition induces significant
stress on the wafer causing significant wafer bowing,
which is a major issue in a 300-mm TSV processing.
For barrier/seed layers in a copper-based integration scheme,
PVD technology offers the most established method for
both via-first and via-last schemes. While the tantalum
(Ta)–tantalum nitride (TaN) barrier is the accepted baseline
barrier based on a natural extension of current dual-damascenecopper
manufacturing technology, titanium (Ti) is being evaluated
as it has the potential for reducing film stress and
manufacturing cost. The key requirements for both via-first
and via-last schemes are to create a continuous barrier and a
nonagglomerated copper seed.
CONCLUSION
TSV is emerging as a method of 3-D integration that offers
designers more freedom and greater functionality with smaller
form factor than that offered by conventional forms of packaging.
Two process flows for this technology are being developed
with minor variations: via-first and via-last. Significant progress
has been made in unit-process optimization and integration, yet
much remains to be done, particularly in such aspects as IC
design, unit process and process integration, defect management,
testing, and reliability. Only if early adopters can realize
satisfactory product value relative to production cost will
TSV become part of mainstream manufacturing. Collaboration
across the entire value chain from on-wafer processing through
bonding and thinning to packaging will be the key to creating
an end-to-end process flow that offers the optimal approach to
commercializing TSV technology.
[attachment=28616]
Abstract
Through-silicon via (TSV) will transition to high
volume production when end-customer value (as exhibited by
functionality, performance, form factor, etc.) are delivered at
equivalent yield and cost.While this has been successfully achieved
for CMOS image sensors (starting with 200 mm), significant work
remains to be done in the TSV value chain (design–materials–
process–packaging–test) in the communication and memory
segments. This paper will address key unit process/processintegration
challenges and highlight recent internal/ partner and
industry findings in the context of TSV manufacturability at
300 mm.
INTRODUCTION
THROUGH-SILICON VIA (TSV) is emerging as a viable
method of joining together stacked integrated circuits
(ICs). Using vertical electrical interconnects that pass through
the die, this approach can reduce interconnect lengths and
enable more compact form factors. These interconnects are
formed by etching vias through the silicon wafer, then filling
them with metal. The silicon die are then stacked and bonded
to each other using the deposited metal. The two TSV methods
commonly used today (but sometimes with different terminology)
involve “via-first/via-middle” and “via-last” process flows.
While the via-last approach appears to be the simpler flow,
with minimum impact to circuit layout, the via-first scheme
(although requiring more changes to interconnect circuit layout)
may ultimately offer the greatest benefits by enabling a
higher density of inputs/outputs (I/Os). This paper examines the
key TSV process technologies and discusses challenges in their
integration for production.
TSV INTEGRATION SCHEMES
In the via-first flow, TSVs are created from the device side
of a full thickness wafer during processing in a wafer fab.
Typically, the vias are 5–10 μm in diameter and 50–100 μm
deep with a nominal aspect ratio of ten. These are also called
iTSVs (interconnect TSVs) as they are made during highdensity
interconnect metallization. In certain instances when
the vias need to be filled with tungsten CVD (instead of the
more common copper), aspect ratios can be up to 20, but this
leads to its own challenges that are outlined later in this paper.
These vias are typically created in the middle of line (after
contact) or during the back-end of line interconnect formation.
Via middle TSVs offer the best flexibility in layout and design.
Interconnect wires fromM1 through Mx may be permitted
to go above them. The dielectric stack on top of the silicon is
also the thinnest at this point in the integration cycle, thereby
simplifying the etch process and minimizing any undercut that
may occur at the interface between the dielectric stack and
silicon. On the other hand, when vias are etched at the very
end of the line, the TSVs have to be etched through a thick
and complex dielectric stack prior to etching the silicon. While
this poses challenges in etching and other processes, it poses
even more challenges for design and layout. One would need to
ensure that the keep-out area around the TSV is maintained all
through the M1–Mx metal stacks, thereby placing unnecessary
constraints in chip layout.
VIA ETCH
Via etch is the first process in the sequence; it sets the foundation
for successful integration and, hence, is very important.
Deep silicon etch can be performed by two different modes of
operation: the Bosch [1] or time-multiplexed gas-modulation
(TMGM) process and the “steady-state” process.
In the Bosch process, the etch reactor alternates between
gases that etch the silicon and gases that deposit a protective
passivation coating on the newly etched feature using
polymerizing chemistries, such as C4F8. The process creates
a series of etched “scallops” in the silicon, which can vary
in size depending on process parameters. With advanced RF
modulation and gas switching techniques, the scallop can be
virtually eliminated.
BARRIER-SEED DEPOSITION, ECD VIA FILL, AND
CHEMICAL–MECHANICAL PLANARIZATION
The most common approach for forming a conductive pathway
through the etched via involves depositing a copper barrier/
seed layer followed by ECD copper fill. A CVD liner followed
by tungsten CVD fill has been demonstrated in a certain TSV
work [3]. However, tungsten CVD deposition induces significant
stress on the wafer causing significant wafer bowing,
which is a major issue in a 300-mm TSV processing.
For barrier/seed layers in a copper-based integration scheme,
PVD technology offers the most established method for
both via-first and via-last schemes. While the tantalum
(Ta)–tantalum nitride (TaN) barrier is the accepted baseline
barrier based on a natural extension of current dual-damascenecopper
manufacturing technology, titanium (Ti) is being evaluated
as it has the potential for reducing film stress and
manufacturing cost. The key requirements for both via-first
and via-last schemes are to create a continuous barrier and a
nonagglomerated copper seed.
CONCLUSION
TSV is emerging as a method of 3-D integration that offers
designers more freedom and greater functionality with smaller
form factor than that offered by conventional forms of packaging.
Two process flows for this technology are being developed
with minor variations: via-first and via-last. Significant progress
has been made in unit-process optimization and integration, yet
much remains to be done, particularly in such aspects as IC
design, unit process and process integration, defect management,
testing, and reliability. Only if early adopters can realize
satisfactory product value relative to production cost will
TSV become part of mainstream manufacturing. Collaboration
across the entire value chain from on-wafer processing through
bonding and thinning to packaging will be the key to creating
an end-to-end process flow that offers the optimal approach to
commercializing TSV technology.