24-07-2012, 01:32 PM
Exploring FPGA Network on Chip Implementations Across Various Application and Network Loads
[attachment=28681]
INTRODUCTION
For FPGA designers, there is always a tendency to look
at standard processor communication paradigms and adopt
them in standard on chip FPGA communication protocols.
This is apparent from Xilinx FPGAs adopting IBM’s PLB bus
architecture to be compatible with their embedded PowerPCs.
But FPGA designers typically keep the arbitration and resource
utilization low for these bus architectures, more so than
processor designers. This simplified implementation is due to
equivalent transistor densities on FPGAs lagging ASICs by an
order of magnitude [1]. The bus architectures utilize so little
logic resources, that they can follow ASIC implementations
fairly close without taking up any sizable amount of onchip
resources.
Network on Chip Reconfigurable Logic Utilization
Using a very popular FPGA in the research community (a
Virtex-II Pro xc2vp30), the LiPaR [2] research project was
able to emulate a 3x3 NoC architecture with 8b datapaths
using 27% of the FPGA resources. This NoC is not a virtual
channel implementation, but does make for a light-weight
router architecture which was the intention of the project.
The open source NoC emulation project, NoCem [3] is the
NoC architecture we based our work from as it is freely
available. Table I shows the utilization of this emulator on
top of a Xilinx Virtex-5 FPGA. Additionally within the table
is the sizing of a extremely lightweight network on chip that
we developed for this research. This implementation will be
further discussed in section III. This comparison is presented
here to show the extreme size difference between network on
chip implementations.
The Cryptographic Accelerator Application
Cracking cryptographic algorithms are well understood
when using simple brute force methods. Typically, this is done
giving the algorithm plain text P1 and retrieving the cypher
text C1. Then, the cryptographic algorithm is cycled with P1
and every possible key K1...Kn until the same cypher text
is generated. From that information, the original key is found
the attack has been successful.
CONCLUSIONS
In this paper, we presented two representative general
purpose NoC implementations (virtual channel and simple
physical channel) to demonstrate how real applications would
perform under a range of network loads. We showed that
a complex NoC architecture does not always lead to better
application performance across a benchmarking and a
cryptographic accelerator application. We also showed that
data-flow applications benefit greatly from virtual channel
implementations demonstrated by the 802.11 transmitter.
FPGAs and reconfigurable computing allow users to configure
and combine pre-existing IP to create complex designs.
From this work, it is clear that the chosen configuration of
a network on chip greatly determines whether a design will
meet area and performance constraints. Hopefully as general
purpose NoC interconnects become available as standard IP,
the underlying NoC architecture will be flexible enough to
support the wide variety of application and network loads that
will exist on these reconfigurable platforms.
[attachment=28681]
INTRODUCTION
For FPGA designers, there is always a tendency to look
at standard processor communication paradigms and adopt
them in standard on chip FPGA communication protocols.
This is apparent from Xilinx FPGAs adopting IBM’s PLB bus
architecture to be compatible with their embedded PowerPCs.
But FPGA designers typically keep the arbitration and resource
utilization low for these bus architectures, more so than
processor designers. This simplified implementation is due to
equivalent transistor densities on FPGAs lagging ASICs by an
order of magnitude [1]. The bus architectures utilize so little
logic resources, that they can follow ASIC implementations
fairly close without taking up any sizable amount of onchip
resources.
Network on Chip Reconfigurable Logic Utilization
Using a very popular FPGA in the research community (a
Virtex-II Pro xc2vp30), the LiPaR [2] research project was
able to emulate a 3x3 NoC architecture with 8b datapaths
using 27% of the FPGA resources. This NoC is not a virtual
channel implementation, but does make for a light-weight
router architecture which was the intention of the project.
The open source NoC emulation project, NoCem [3] is the
NoC architecture we based our work from as it is freely
available. Table I shows the utilization of this emulator on
top of a Xilinx Virtex-5 FPGA. Additionally within the table
is the sizing of a extremely lightweight network on chip that
we developed for this research. This implementation will be
further discussed in section III. This comparison is presented
here to show the extreme size difference between network on
chip implementations.
The Cryptographic Accelerator Application
Cracking cryptographic algorithms are well understood
when using simple brute force methods. Typically, this is done
giving the algorithm plain text P1 and retrieving the cypher
text C1. Then, the cryptographic algorithm is cycled with P1
and every possible key K1...Kn until the same cypher text
is generated. From that information, the original key is found
the attack has been successful.
CONCLUSIONS
In this paper, we presented two representative general
purpose NoC implementations (virtual channel and simple
physical channel) to demonstrate how real applications would
perform under a range of network loads. We showed that
a complex NoC architecture does not always lead to better
application performance across a benchmarking and a
cryptographic accelerator application. We also showed that
data-flow applications benefit greatly from virtual channel
implementations demonstrated by the 802.11 transmitter.
FPGAs and reconfigurable computing allow users to configure
and combine pre-existing IP to create complex designs.
From this work, it is clear that the chosen configuration of
a network on chip greatly determines whether a design will
meet area and performance constraints. Hopefully as general
purpose NoC interconnects become available as standard IP,
the underlying NoC architecture will be flexible enough to
support the wide variety of application and network loads that
will exist on these reconfigurable platforms.