25-07-2012, 11:21 AM
Simulation and Verification of Self Test 16-Bit Processor
[attachment=28819]
INTRODUCTION
The authors in [1] presented a design methodology of a single
clock cycle Processor using VHDL to ease the description,
verification, simulation and hardware realization. The RISC
processor has fixed-length of 32-bit instructions based on three
different formats: R-format, I-format and J-format, and 32-bit
general-purpose registers with memory word of 32-bit. The
processor is separated into five stages: instruction fetch,
instruction decode, execution, data memory and write back. The
control unit controls the operations performed in these stages.
All the modules in the design are coded in VHDL, as it is very
useful tool with its concept of concurrency to cope with the
parallelism of digital hardware. The authors in [2] proposed a
VHDL based rapid prototyping approach to simulate,
synthesize, and implement a prototype computer system using
commercial CAD tools, a Meta assembler, a C compiler, and
FPGAs in a hardware emulator. The use of VHDL for the design
and implementation of a CPU structure has been presented in
[3]. Initially the CPU is described at the behavioral level.
DESIGN OF 16-BIT PROCESSOR
Usually, all classical design methods involve one or more PCBs
(printed circuit board) that contain many chips together with
other components. Development of these products starts with the
definition of the overall structure. After that the required
integrated circuits chips are selected followed by the PCBs that
house and connect the chips together are designed. Since the
complexity of circuits implemented on individual chips and on
the circuit boards is usually very high, it is very much essential
to make use of Xilinx software [7].
ARCHITECTURE
The architecture of proposed 16-bit Processor is shown in Fig.2
which consists of processor block and memory block
communicating through data bus, an address bus and a few
control lines [8-10]. The architecture of the 16-bit processor is
designed based on three 16-bit instruction formats R-format, Iformat
and J-format. The design of this processor consists of 16-
bit instructions and 16-bit data path. The implementation of
processor performs fetch, decode, and execute operation. The
fetch stage obtains the requested instruction from memory. The
operation of the fetch stage starts when the program counter
(PC) a 16-bit register is sent out to fetch the instruction from
memory into the instruction register (IR) and the PC is
incremented to address the next sequential instruction.
Data path
There are 16 number of 16 bit registers in register file. So
Register file of data path consists of 4-bit address bus and 16-bit
data bus. This is a two port register file which can perform two
simultaneous read and one write operation. It contains sixteen
16-bit general purpose registers. The registers are named R0
through R15. When the Register Write signal is high, a write
operation is performed to the register indicated by the write
address, otherwise it outputs the value contained in the register
indicated by the read address. The ALU is responsible for all
arithmetic and logic operations that take place within the
processor. These operations can have one operand or two, with
these values coming from either the register file or from the
immediate value from the instruction directly.
SIMULATION AND DISCUSSION
We have synthesized and simulated the VHDL code of the
proposed processor using Xilinx Integrated Software
Environment tool (Version 10.1). The synthesis results and
simulation results of processor are presented for justification.
The proposed 16 bit RISC processor is coded with VHDL (very
high speed integrated circuit hardware description language).
Using Xilinx ISE 10.1 software the code is tested and checked
for error. When there is no error, the code is synthesized and
simulated using Xilinx ISE 10.1 software. The synthesis and
simulation results are compared with the theoretical results.
Before the start of simulation, the memory is loaded by writing
the instructions and data into the memory.
[attachment=28819]
INTRODUCTION
The authors in [1] presented a design methodology of a single
clock cycle Processor using VHDL to ease the description,
verification, simulation and hardware realization. The RISC
processor has fixed-length of 32-bit instructions based on three
different formats: R-format, I-format and J-format, and 32-bit
general-purpose registers with memory word of 32-bit. The
processor is separated into five stages: instruction fetch,
instruction decode, execution, data memory and write back. The
control unit controls the operations performed in these stages.
All the modules in the design are coded in VHDL, as it is very
useful tool with its concept of concurrency to cope with the
parallelism of digital hardware. The authors in [2] proposed a
VHDL based rapid prototyping approach to simulate,
synthesize, and implement a prototype computer system using
commercial CAD tools, a Meta assembler, a C compiler, and
FPGAs in a hardware emulator. The use of VHDL for the design
and implementation of a CPU structure has been presented in
[3]. Initially the CPU is described at the behavioral level.
DESIGN OF 16-BIT PROCESSOR
Usually, all classical design methods involve one or more PCBs
(printed circuit board) that contain many chips together with
other components. Development of these products starts with the
definition of the overall structure. After that the required
integrated circuits chips are selected followed by the PCBs that
house and connect the chips together are designed. Since the
complexity of circuits implemented on individual chips and on
the circuit boards is usually very high, it is very much essential
to make use of Xilinx software [7].
ARCHITECTURE
The architecture of proposed 16-bit Processor is shown in Fig.2
which consists of processor block and memory block
communicating through data bus, an address bus and a few
control lines [8-10]. The architecture of the 16-bit processor is
designed based on three 16-bit instruction formats R-format, Iformat
and J-format. The design of this processor consists of 16-
bit instructions and 16-bit data path. The implementation of
processor performs fetch, decode, and execute operation. The
fetch stage obtains the requested instruction from memory. The
operation of the fetch stage starts when the program counter
(PC) a 16-bit register is sent out to fetch the instruction from
memory into the instruction register (IR) and the PC is
incremented to address the next sequential instruction.
Data path
There are 16 number of 16 bit registers in register file. So
Register file of data path consists of 4-bit address bus and 16-bit
data bus. This is a two port register file which can perform two
simultaneous read and one write operation. It contains sixteen
16-bit general purpose registers. The registers are named R0
through R15. When the Register Write signal is high, a write
operation is performed to the register indicated by the write
address, otherwise it outputs the value contained in the register
indicated by the read address. The ALU is responsible for all
arithmetic and logic operations that take place within the
processor. These operations can have one operand or two, with
these values coming from either the register file or from the
immediate value from the instruction directly.
SIMULATION AND DISCUSSION
We have synthesized and simulated the VHDL code of the
proposed processor using Xilinx Integrated Software
Environment tool (Version 10.1). The synthesis results and
simulation results of processor are presented for justification.
The proposed 16 bit RISC processor is coded with VHDL (very
high speed integrated circuit hardware description language).
Using Xilinx ISE 10.1 software the code is tested and checked
for error. When there is no error, the code is synthesized and
simulated using Xilinx ISE 10.1 software. The synthesis and
simulation results are compared with the theoretical results.
Before the start of simulation, the memory is loaded by writing
the instructions and data into the memory.