25-07-2012, 04:46 PM
A Median Filter FPGA with Harvard Architecture
[attachment=28963]
INTRODUCTION
image processing technology has been widely used in
communications systems, radar, biomedical electronics,
electronic test equipment, industrial testing and all
aspects of our live [1]. With the development of computer
technology, artificial intelligence and new architecture, the
rapid of image processing is faster than ever [2]. The image
quality is higher than ever. Now more and more used analog
processing can’t meet the demand. For this phenomenon, this
paper designs a new median filter chip with FPGA [3].
The chip uses the Harvard Structure on the main data
processing to reduce the waiting time and to increase data
processing. This chip can give the clearer and smoother
image than ever. The Verilog HDL code is downloaded in
epf6016tc144-2. The chip is the hardware of median filter.
The way is better than the way of soft processor [4].
Hardware-based algorithms have large economic benefits and
significant performance improvements.
DESIGN PRINCIPLES
A. Median Filter Algorithm
The median filter data are in a sliding window containing
the odd point. That point datum in the middle is replaced of
the average of the gray value in the window.
For example, there is a one-dimensional sequence of f1,
f2,…，fn. The filter window length is m (m is odd). The
input data are fi-v,…fi-1,fi,fi＋1,…and fi+v . Here, the value
of i is the center of the window.
CHIP
The median filter is a nonlinear filter [5]. Because it does
not require the statistical characteristics of an image, it is
more convenient than ever [6]. With the filter hardware
algorithm, the application is more convenient and flexible
than with the Von Neumann Architecture.
Based on median filter algorithm and hardware
architecture, the chip is designed in Verilog-HDL. The chip
can process an image with anti-color, histogram equalization,
median filter, sharpening, compression and other ways. So
the FPGA is selected Altera Corporation epf6016tc144-2
devices. The FPGA has 1,320 units, 6 EABs. In this chip, the
part of median filter can’t outpace 20% of the chip.
THE SIMULATION RESULTS
The test image is Fig.4 of 256*256. The I/O data of the
median filter are sent to show like Fig.4 Balancing the
original image and the image used the chip, we can found that
except the noise in the original boundary basically disappears,
and the image becomes bright. So an image can be clearly
observed in detail.
Fig.4. The images before and after the median filter DSP
Some data of the image are in the table I. The noise “0”
changes to “255” to meet the goal datum [7].
Using the chip, the processing time is 2.37μs. The time is
less than the time 2.73μs of the chip with Von Neumann
Architecture. In short, the chip basically completes the design
task.
[attachment=28963]
INTRODUCTION
image processing technology has been widely used in
communications systems, radar, biomedical electronics,
electronic test equipment, industrial testing and all
aspects of our live [1]. With the development of computer
technology, artificial intelligence and new architecture, the
rapid of image processing is faster than ever [2]. The image
quality is higher than ever. Now more and more used analog
processing can’t meet the demand. For this phenomenon, this
paper designs a new median filter chip with FPGA [3].
The chip uses the Harvard Structure on the main data
processing to reduce the waiting time and to increase data
processing. This chip can give the clearer and smoother
image than ever. The Verilog HDL code is downloaded in
epf6016tc144-2. The chip is the hardware of median filter.
The way is better than the way of soft processor [4].
Hardware-based algorithms have large economic benefits and
significant performance improvements.
DESIGN PRINCIPLES
A. Median Filter Algorithm
The median filter data are in a sliding window containing
the odd point. That point datum in the middle is replaced of
the average of the gray value in the window.
For example, there is a one-dimensional sequence of f1,
f2,…，fn. The filter window length is m (m is odd). The
input data are fi-v,…fi-1,fi,fi＋1,…and fi+v . Here, the value
of i is the center of the window.
CHIP
The median filter is a nonlinear filter [5]. Because it does
not require the statistical characteristics of an image, it is
more convenient than ever [6]. With the filter hardware
algorithm, the application is more convenient and flexible
than with the Von Neumann Architecture.
Based on median filter algorithm and hardware
architecture, the chip is designed in Verilog-HDL. The chip
can process an image with anti-color, histogram equalization,
median filter, sharpening, compression and other ways. So
the FPGA is selected Altera Corporation epf6016tc144-2
devices. The FPGA has 1,320 units, 6 EABs. In this chip, the
part of median filter can’t outpace 20% of the chip.
THE SIMULATION RESULTS
The test image is Fig.4 of 256*256. The I/O data of the
median filter are sent to show like Fig.4 Balancing the
original image and the image used the chip, we can found that
except the noise in the original boundary basically disappears,
and the image becomes bright. So an image can be clearly
observed in detail.
Fig.4. The images before and after the median filter DSP
Some data of the image are in the table I. The noise “0”
changes to “255” to meet the goal datum [7].
Using the chip, the processing time is 2.37μs. The time is
less than the time 2.73μs of the chip with Von Neumann
Architecture. In short, the chip basically completes the design
task.