27-07-2012, 03:06 PM
CMOS ANALOG-to-DIGITAL CONVERTER
[attachment=29284]
DESCRIPTION
The ADS7805 is a complete 16-bit sampling, Analog-to-
Digital (A/D) converter using state-of-the-art CMOS structures.
It contains a complete 16-bit, capacitor-based, Successive
Approximation Register (SAR) A/D converter with
Sample-and-Hold (S/H), reference, clock, interface for microprocessor
use, and 3-state output drivers.
The ADS7805 is specified at a 100kHz sampling rate and
ensured over the full temperature range. Laser-trimmed
scaling resistors provide an industry-standard ±10V input
range while the innovative design allows operation from a
single +5V supply, with power dissipation under 100mW.
The ADS7805 is available in a 0.3" DIP-28 and an SO-28
package. Both are fully specified for operation over the
industrial –25°C to +85°C range; however, they will function
over the –40°C to +85C temperature range.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7805 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (7μs max) will initiate a conversion. BUSY
(pin 26) will go LOW and stay LOW until the conversion is
completed and the output registers are updated. Data will be
output in Binary Two’s Complement with the MSB on pin 6.
BUSY going HIGH can be used to latch the data. All convert
commands will be ignored while BUSY is LOW.
The ADS7805 will begin tracking the input signal at the end
of the conversion. Allowing 10μs between convert commands
assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate
for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the “Calibration”
section).
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) LOW for a
minimum of 40ns immediately puts the sample-and-hold of
the ADS7805 in the hold state and starts conversion ‘n’.
BUSY (pin 26) will go LOW and stay LOW until conversion
‘n’ is completed and the internal output register has been
updated. All new convert commands during BUSY LOW will
be ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without sufficient
time to acquire a new signal.
READING DATA
The ADS7805 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS (pin
25) is LOW. Any other combination of CS and R/C will tristate
the parallel output. Valid conversion data can be read
in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both
bytes within one conversion cycle. Refer to Table III for ideal
output codes and Figure 2 for bit locations relative to the
state of BYTE.
INPUT RANGES
The ADS7805 offers a standard ±10V input range. Figure 6
shows the necessary circuit connections for the ADS7805
with and without hardware trim. Offset and full-scale error(1)
specifications are tested and specified with the fixed resistors
shown in Figure 6b. Adjustments for offset and gain are
described in the “Calibration” section of this data sheet.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate
for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the “Calibration”
section).
The nominal input impedance of 23kΩ results from the combination
of the internal resistor network shown on the front page
of the product data sheet and the external resistors. The input
resistor divider network provides inherent overvoltage protection
ensured to at least ±25V. The 1% resistors used for the
external circuitry do not compromise the accuracy or drift of the
converter. They have little influence relative to the internal
resistors, and tighter tolerances are not required.
NOTE: (1) Full-scale error includes offset and gain errors measured at both +FS
and –FS.
CALIBRATION
The ADS7805 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain. To achieve optimum performance,
several iterations may be required.
HARDWARE CALIBRATION
To calibrate the offset and gain of the ADS7805, install the
proper resistors and potentiometers as shown in Figure 6a.
The calibration range is ±15mV for the offset and ±60mV for
the gain.
[attachment=29284]
DESCRIPTION
The ADS7805 is a complete 16-bit sampling, Analog-to-
Digital (A/D) converter using state-of-the-art CMOS structures.
It contains a complete 16-bit, capacitor-based, Successive
Approximation Register (SAR) A/D converter with
Sample-and-Hold (S/H), reference, clock, interface for microprocessor
use, and 3-state output drivers.
The ADS7805 is specified at a 100kHz sampling rate and
ensured over the full temperature range. Laser-trimmed
scaling resistors provide an industry-standard ±10V input
range while the innovative design allows operation from a
single +5V supply, with power dissipation under 100mW.
The ADS7805 is available in a 0.3" DIP-28 and an SO-28
package. Both are fully specified for operation over the
industrial –25°C to +85°C range; however, they will function
over the –40°C to +85C temperature range.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7805 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (7μs max) will initiate a conversion. BUSY
(pin 26) will go LOW and stay LOW until the conversion is
completed and the output registers are updated. Data will be
output in Binary Two’s Complement with the MSB on pin 6.
BUSY going HIGH can be used to latch the data. All convert
commands will be ignored while BUSY is LOW.
The ADS7805 will begin tracking the input signal at the end
of the conversion. Allowing 10μs between convert commands
assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate
for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the “Calibration”
section).
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) LOW for a
minimum of 40ns immediately puts the sample-and-hold of
the ADS7805 in the hold state and starts conversion ‘n’.
BUSY (pin 26) will go LOW and stay LOW until conversion
‘n’ is completed and the internal output register has been
updated. All new convert commands during BUSY LOW will
be ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without sufficient
time to acquire a new signal.
READING DATA
The ADS7805 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS (pin
25) is LOW. Any other combination of CS and R/C will tristate
the parallel output. Valid conversion data can be read
in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both
bytes within one conversion cycle. Refer to Table III for ideal
output codes and Figure 2 for bit locations relative to the
state of BYTE.
INPUT RANGES
The ADS7805 offers a standard ±10V input range. Figure 6
shows the necessary circuit connections for the ADS7805
with and without hardware trim. Offset and full-scale error(1)
specifications are tested and specified with the fixed resistors
shown in Figure 6b. Adjustments for offset and gain are
described in the “Calibration” section of this data sheet.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate
for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the “Calibration”
section).
The nominal input impedance of 23kΩ results from the combination
of the internal resistor network shown on the front page
of the product data sheet and the external resistors. The input
resistor divider network provides inherent overvoltage protection
ensured to at least ±25V. The 1% resistors used for the
external circuitry do not compromise the accuracy or drift of the
converter. They have little influence relative to the internal
resistors, and tighter tolerances are not required.
NOTE: (1) Full-scale error includes offset and gain errors measured at both +FS
and –FS.
CALIBRATION
The ADS7805 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain. To achieve optimum performance,
several iterations may be required.
HARDWARE CALIBRATION
To calibrate the offset and gain of the ADS7805, install the
proper resistors and potentiometers as shown in Figure 6a.
The calibration range is ±15mV for the offset and ±60mV for
the gain.