30-07-2012, 11:29 AM
DIGITAL DESIGN WITH VHDL
[attachment=29467]
INTRODUCTION
HISTORY
VHDL (VHSIC Hardware Description Language) is a language for describing
hardware. Its requirement emerged during the VHSIC development program of the US
Department of Defense. The department organized a work shop in 1981 to lay down the
specifications of a language which could describe hardware at various levels of
abstractions, could generate test signals and record responses, and could act as a medium
of information exchange between the chip foundries and the CAD tool operators.
However, due to military restrictions, it remained classified till 1985. There was a large
participation of the private sector electronics industry in the development of the language.
It felt that there was a need to make the language industry standard. In 1985, the DOD
granted a permission to hand over the specs to IEEE. Subsequently IEEE released the
IEEE 1076/A standard in 1987. It was later revised in 1993. The 1993 revisions are
minor and many of the simulation and synthesis tools have not yet adopted them.
TOP DOWN.
In this approach, first the top-level behavior is designed and then it is partitioned it into
smaller subsystems and then sub subsystems till it is reduced to simple components.
Behavioral description is suitable here. It has been observed that this approach is suitable
for large designs, typically involving more than 10000 basic gates. Many FPGA based
designs follow this approach.
BOTTOM UP.
This is the traditional schematic based approach. It is used when a library of known low
level components such as 74XX TTL is available. You build medium subsystems from
them and then finally interconnect them to realize the overall system. This approach is
suitable for small systems using standard components.
MIXED.
This approach is similar to the top down approach in sense that you start from top level.
But here you don’t go right up to the component level. You can stop when you can find
suitable medium level entities for realizing the design. A library of medium level
components is prepared for this purpose, using the bottom up approach. This approach is
suitable for ASIC design where vendor supplied cell libraries are available.
Design process: -
Digital system design starts from the user specifications. The specifications define
the terminal behavior of the proposed system and provide a natural language description
of how the input signals are transformed into outputs. Translation from this stage to
silicon is a giant step. To make it manageable, it has to be broken down into several
smaller steps as shown in Figure 1.1. A translation from a higher level of abstraction to a
lower level is SYNTHESIS and a study of the behavior of a lower level model in terms of
the higher level description is ANALYSIS.
Overview of VHDL
Copyright CMR Design Automation P Ltd, E 534 Greater Kailash II, New Delhi 110048
Suppliers of ExcelVHDL, Speedwave VHDL, Fintronic Verilog, Specman ,
This manual specially created for EFY & IT Magazine CD
VHDL syntax is very close to that of ADA. The VHDL literature uses terms like
objects and classes but VHDL is not a fully object oriented language. It incorporates
some features of object oriented languages like C++ or Object Pascal, namely functions
with default parameters, function overloading and operator overloading. The “classes” in
VHDL are more like structures of C++ because they are not allowed to have function
members. In VHDL, anything that occupies memory is called an “Object”. These objects
have to be derived from some predefined classes. However, for defining classes, the
keyword “TYPE” is used instead of “CLASS”. This is similar to the Object Pascal
convention. “Inheritance”, which is an important OOPS feature, is not supported by
VHDL as it complicates synthesis.
[attachment=29467]
INTRODUCTION
HISTORY
VHDL (VHSIC Hardware Description Language) is a language for describing
hardware. Its requirement emerged during the VHSIC development program of the US
Department of Defense. The department organized a work shop in 1981 to lay down the
specifications of a language which could describe hardware at various levels of
abstractions, could generate test signals and record responses, and could act as a medium
of information exchange between the chip foundries and the CAD tool operators.
However, due to military restrictions, it remained classified till 1985. There was a large
participation of the private sector electronics industry in the development of the language.
It felt that there was a need to make the language industry standard. In 1985, the DOD
granted a permission to hand over the specs to IEEE. Subsequently IEEE released the
IEEE 1076/A standard in 1987. It was later revised in 1993. The 1993 revisions are
minor and many of the simulation and synthesis tools have not yet adopted them.
TOP DOWN.
In this approach, first the top-level behavior is designed and then it is partitioned it into
smaller subsystems and then sub subsystems till it is reduced to simple components.
Behavioral description is suitable here. It has been observed that this approach is suitable
for large designs, typically involving more than 10000 basic gates. Many FPGA based
designs follow this approach.
BOTTOM UP.
This is the traditional schematic based approach. It is used when a library of known low
level components such as 74XX TTL is available. You build medium subsystems from
them and then finally interconnect them to realize the overall system. This approach is
suitable for small systems using standard components.
MIXED.
This approach is similar to the top down approach in sense that you start from top level.
But here you don’t go right up to the component level. You can stop when you can find
suitable medium level entities for realizing the design. A library of medium level
components is prepared for this purpose, using the bottom up approach. This approach is
suitable for ASIC design where vendor supplied cell libraries are available.
Design process: -
Digital system design starts from the user specifications. The specifications define
the terminal behavior of the proposed system and provide a natural language description
of how the input signals are transformed into outputs. Translation from this stage to
silicon is a giant step. To make it manageable, it has to be broken down into several
smaller steps as shown in Figure 1.1. A translation from a higher level of abstraction to a
lower level is SYNTHESIS and a study of the behavior of a lower level model in terms of
the higher level description is ANALYSIS.
Overview of VHDL
Copyright CMR Design Automation P Ltd, E 534 Greater Kailash II, New Delhi 110048
Suppliers of ExcelVHDL, Speedwave VHDL, Fintronic Verilog, Specman ,
This manual specially created for EFY & IT Magazine CD
VHDL syntax is very close to that of ADA. The VHDL literature uses terms like
objects and classes but VHDL is not a fully object oriented language. It incorporates
some features of object oriented languages like C++ or Object Pascal, namely functions
with default parameters, function overloading and operator overloading. The “classes” in
VHDL are more like structures of C++ because they are not allowed to have function
members. In VHDL, anything that occupies memory is called an “Object”. These objects
have to be derived from some predefined classes. However, for defining classes, the
keyword “TYPE” is used instead of “CLASS”. This is similar to the Object Pascal
convention. “Inheritance”, which is an important OOPS feature, is not supported by
VHDL as it complicates synthesis.