31-07-2012, 01:25 PM
VLSI Implementation of Image Segmentation with Resource Optimized Adaptive Median Filter
[attachment=29695]
ABSTRACT
FPGA (Field Programmable Gate Array) is utilized to realize
the image segmentation. We describe a newfangled method for
segmentation of 2-D imagery that uses resource optimized
adaptive median filter for image enhancement. A pipelined
implementation on FPGA for this algorithm is designed. Sobel
operator is used for edge detection. Processed results of test
images are presented to illustrate the performance capabilities of
the proposed method. The FPGA resource utilization for
proposed architecture is 50% less compared to the Adaptive
Median Filter and the variation in the final picture quality is
only + 1dB PSNR.
INTRODUCTION
Implementing hardware design in FPGAs (Field Programmable
Gate Arrays) is a formidable task. There is more than one way
to implement the digital f ilter. Based on the design specification,
careful choice of implementation method and tools can save a
lot of time and work. Most of the algorithms are
computationally intensive, so it is desirable to implement them
in high performance reconfigurable systems. Recently, FPGA
technology has become a viable target for the implementation of
algorithms for image processing. Firstly, the algorithm is
simulated in MATLAB, and then the same is implemented into
VHDL with the help of Xilinx ISE and the ModelSim
simulation results are verified with MATLAB results.
RELATED WORK
Conventionally, the Gaussian filter is used for the image
enhancement purpose followed by first differentiation of it for
the edge-detection. From simulation results, we observed that
the AMF (Adaptive Median Filter) gives better results as
compared to it. Therefore we propose to use the adaptive
median filter instead of the Gaussian and median filter. We have
proposed implementation of a resource opt imized adaptive
median filter. It is well known that the Sobel-edge operator
gives expected result for edge detection; hence we propose to
use the Sobel operator instead of first differentiation of the f ilter
used in the first step.
CONCLUSION
The integral components of the implementation are image
smoothening by adaptive median filter and edge-detection with
Sobel-operator. Resource optimized hardware implementation
of adaptive median filter is presented. The resource utilization
for proposed architecture is 50% less compared to the Adaptive
Median Filter and the variation in the f inal picture quality is only
+ 1dB PSNR.
Further, a version of the alpha max plus beta min algorithm is
devised to find the edge-strength in edge-detection module. This
contribution presented reduction in one multiplier for
implementation in FPGA hardware mainly to solve resource
issue. The proposed strategy has been conducted to implement
FPGA based square-root of sum of squares successfully. The
results have shown that proposed method has maximum 9%
deviation as compared to exact value.
[attachment=29695]
ABSTRACT
FPGA (Field Programmable Gate Array) is utilized to realize
the image segmentation. We describe a newfangled method for
segmentation of 2-D imagery that uses resource optimized
adaptive median filter for image enhancement. A pipelined
implementation on FPGA for this algorithm is designed. Sobel
operator is used for edge detection. Processed results of test
images are presented to illustrate the performance capabilities of
the proposed method. The FPGA resource utilization for
proposed architecture is 50% less compared to the Adaptive
Median Filter and the variation in the final picture quality is
only + 1dB PSNR.
INTRODUCTION
Implementing hardware design in FPGAs (Field Programmable
Gate Arrays) is a formidable task. There is more than one way
to implement the digital f ilter. Based on the design specification,
careful choice of implementation method and tools can save a
lot of time and work. Most of the algorithms are
computationally intensive, so it is desirable to implement them
in high performance reconfigurable systems. Recently, FPGA
technology has become a viable target for the implementation of
algorithms for image processing. Firstly, the algorithm is
simulated in MATLAB, and then the same is implemented into
VHDL with the help of Xilinx ISE and the ModelSim
simulation results are verified with MATLAB results.
RELATED WORK
Conventionally, the Gaussian filter is used for the image
enhancement purpose followed by first differentiation of it for
the edge-detection. From simulation results, we observed that
the AMF (Adaptive Median Filter) gives better results as
compared to it. Therefore we propose to use the adaptive
median filter instead of the Gaussian and median filter. We have
proposed implementation of a resource opt imized adaptive
median filter. It is well known that the Sobel-edge operator
gives expected result for edge detection; hence we propose to
use the Sobel operator instead of first differentiation of the f ilter
used in the first step.
CONCLUSION
The integral components of the implementation are image
smoothening by adaptive median filter and edge-detection with
Sobel-operator. Resource optimized hardware implementation
of adaptive median filter is presented. The resource utilization
for proposed architecture is 50% less compared to the Adaptive
Median Filter and the variation in the f inal picture quality is only
+ 1dB PSNR.
Further, a version of the alpha max plus beta min algorithm is
devised to find the edge-strength in edge-detection module. This
contribution presented reduction in one multiplier for
implementation in FPGA hardware mainly to solve resource
issue. The proposed strategy has been conducted to implement
FPGA based square-root of sum of squares successfully. The
results have shown that proposed method has maximum 9%
deviation as compared to exact value.