01-08-2012, 03:23 PM
An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines
[attachment=29905]
Abstract
In this paper, we present a transmission-line-based model developed
to accurately describe the power and ground-line interconnections
of modern digital ASICs. The proposed model employs transmission lines
as the core component to properly describe both the capacitive and inductive
behavior of the metal lines. In addition, the nonlinear frequency dependence
of the line resistance, due to the skin-effect, is modeled with an additional
lumped model. The model is completely derived from measurement
data and allows describing both in-house and third-party ASICs.
INTRODUCTION
Modern communication systems demand a continuous increase in
bandwidth/data-rates and operating frequencies. In order to accomplish
this goal, an increase in the level of parallelism of CMOS designs at the
IC level is required (i.e., wide binary words and consequently wide bus
structures). At the same time, the reduction of the propagation delay
of a single output buffer induces a higher current during the transition.
Thus, simultaneous switching of different output buffers will draw
large currents in short time intervals (e.g., current pulses) from the I/O
power lines (VDDQ/GNDQ), generating a large voltage surge/droop,
which is referred to as power or ground bounce. [1]–[4]. To model interconnections,
an
[attachment=29905]
Abstract
In this paper, we present a transmission-line-based model developed
to accurately describe the power and ground-line interconnections
of modern digital ASICs. The proposed model employs transmission lines
as the core component to properly describe both the capacitive and inductive
behavior of the metal lines. In addition, the nonlinear frequency dependence
of the line resistance, due to the skin-effect, is modeled with an additional
lumped model. The model is completely derived from measurement
data and allows describing both in-house and third-party ASICs.
INTRODUCTION
Modern communication systems demand a continuous increase in
bandwidth/data-rates and operating frequencies. In order to accomplish
this goal, an increase in the level of parallelism of CMOS designs at the
IC level is required (i.e., wide binary words and consequently wide bus
structures). At the same time, the reduction of the propagation delay
of a single output buffer induces a higher current during the transition.
Thus, simultaneous switching of different output buffers will draw
large currents in short time intervals (e.g., current pulses) from the I/O
power lines (VDDQ/GNDQ), generating a large voltage surge/droop,
which is referred to as power or ground bounce. [1]–[4]. To model interconnections,
an