08-08-2012, 04:22 PM
Timing diagram of 8085
[attachment=30641]
INTRODUCTION
Timing diagram is the display of initiation of read/write and transfer of data operations under
the control of 3-status signals IO / M , S1, and S0. As the heartbeat is required for the survival
of the human being, the CLK is required for the proper operation of different sections of the
microprocessors. All actions in the microprocessor is controlled by either leading or trailing edge
of the clock. If I ask a man to bring 6-bags of wheat, each weighing 100 kg, he may take 6-times
to perform this task in going and bringing it. A stronger man might perform the same task in 3-
times only. Thus, it depends on the strength of the man to finish the job quickly or slowly. Here,
we can assume both weaker and strong men as machine. The weaker man has taken 6-machine
cycle (6-times going and coming with one bag each time) to execute the job where as the stronger
man has taken only 3-machine cycle for the same job. Similarly, a machine may execute one
instruction in as many as 3-machine cycles while the other machine can take only one machine
cycle to execute the same instruction. Thus, the machine that has taken only one machine cycle
is efficient than the one taking 3-machine cycle. Each machine cycle is composed of many clock
cycle. Since, the data and instructions, both are stored in the memory, the μP performs fetch
operation to read the instruction or data and then execute the instruction. The μP in doing so may
take several cycles to perform fetch and execute operation. The 3-status signals : IO / M, S1, and
S0 are generated at the beginning of each machine cycle. The unique combination of these 3-status
signals identify read or write operation and remain valid for the duration of the cycle. Table-5.1(a)
shows details of the unique combination of these status signals to identify different machine cycles.
Thus, time taken by any μP to execute one instruction is calculated in terms of the clock period.
PROCESSOR CYCLE
The function of the microprocessor is divided into fetch and execute cycle of any instruction
of a program. The program is nothing but number of instructions stored in the memory in sequence.
In the normal process of operation, the microprocessor fetches (receives or reads) and
executes one instruction at a time in the sequence until it executes the halt (HLT) instruction.
Thus, an instruction cycle is defined as the time required to fetch and execute an instruction. For
executing any program, basically 2-steps are followed sequentially with the help of clocks
• Fetch, and
• Execute.
The time taken by the μP in performing the fetch and execute operations are called fetch
and execute cycle. Thus, sum of the fetch and execute cycle is called the instruction cycle as
indicated in Fig. 5.2 (a).
Opcode Fetch
A microprocessor either reads or writes to the memory or I/O devices. The time taken to
read or write for any instruction must be known in terms of the μP clock. The 1st step in
communicating between the microprocessor and memory is reading from the memory. This reading
process is called opcode fetch. The process of opcode fetch operation requires minimum 4-
clock cycles T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every instruction.
In order to differentiate between the data byte pertaining to an opcode or an address, the
machine cycle takes help of the status signal IO/M, S1, and S0. The IO/M = 0 indicates
memory operation and S1 = S0 = 1 indicates Opcode fetch operation.
[attachment=30641]
INTRODUCTION
Timing diagram is the display of initiation of read/write and transfer of data operations under
the control of 3-status signals IO / M , S1, and S0. As the heartbeat is required for the survival
of the human being, the CLK is required for the proper operation of different sections of the
microprocessors. All actions in the microprocessor is controlled by either leading or trailing edge
of the clock. If I ask a man to bring 6-bags of wheat, each weighing 100 kg, he may take 6-times
to perform this task in going and bringing it. A stronger man might perform the same task in 3-
times only. Thus, it depends on the strength of the man to finish the job quickly or slowly. Here,
we can assume both weaker and strong men as machine. The weaker man has taken 6-machine
cycle (6-times going and coming with one bag each time) to execute the job where as the stronger
man has taken only 3-machine cycle for the same job. Similarly, a machine may execute one
instruction in as many as 3-machine cycles while the other machine can take only one machine
cycle to execute the same instruction. Thus, the machine that has taken only one machine cycle
is efficient than the one taking 3-machine cycle. Each machine cycle is composed of many clock
cycle. Since, the data and instructions, both are stored in the memory, the μP performs fetch
operation to read the instruction or data and then execute the instruction. The μP in doing so may
take several cycles to perform fetch and execute operation. The 3-status signals : IO / M, S1, and
S0 are generated at the beginning of each machine cycle. The unique combination of these 3-status
signals identify read or write operation and remain valid for the duration of the cycle. Table-5.1(a)
shows details of the unique combination of these status signals to identify different machine cycles.
Thus, time taken by any μP to execute one instruction is calculated in terms of the clock period.
PROCESSOR CYCLE
The function of the microprocessor is divided into fetch and execute cycle of any instruction
of a program. The program is nothing but number of instructions stored in the memory in sequence.
In the normal process of operation, the microprocessor fetches (receives or reads) and
executes one instruction at a time in the sequence until it executes the halt (HLT) instruction.
Thus, an instruction cycle is defined as the time required to fetch and execute an instruction. For
executing any program, basically 2-steps are followed sequentially with the help of clocks
• Fetch, and
• Execute.
The time taken by the μP in performing the fetch and execute operations are called fetch
and execute cycle. Thus, sum of the fetch and execute cycle is called the instruction cycle as
indicated in Fig. 5.2 (a).
Opcode Fetch
A microprocessor either reads or writes to the memory or I/O devices. The time taken to
read or write for any instruction must be known in terms of the μP clock. The 1st step in
communicating between the microprocessor and memory is reading from the memory. This reading
process is called opcode fetch. The process of opcode fetch operation requires minimum 4-
clock cycles T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every instruction.
In order to differentiate between the data byte pertaining to an opcode or an address, the
machine cycle takes help of the status signal IO/M, S1, and S0. The IO/M = 0 indicates
memory operation and S1 = S0 = 1 indicates Opcode fetch operation.