09-08-2012, 10:36 AM
8051 Core Specification
[attachment=30690]
Introduction
MCS-51 family, originally designed by Intel in the 1980’s
Used in a large percentage of embedded systems
Includes several on-chip peripherals, like timers and counters
128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory
Features (1/2)
8-bit CPU optimized for control applications
Extensive Boolean processing (single-bit logic) capabilities
64K Program Memory address space
64K Data Memory address space
Up to 4K bytes of on-chip Program Memory
128 bytes of on-chip Data RAM
32 bi-directional and individually addressable I/O lines
Two 16-bit timer/counters
6-source/5-vector interrupt structure with two priority levels
Memory Organization (1/3)
Logical separation of program and data memory
Separate address spaces for Program (ROM) and Data (RAM) Memory
Allow Data Memory to be accessed by 8-bit addresses quickly and manipulated by 8-bit CPU
Program Memory
Only be read, not written to
The address space is 16-bit, so maximum of 64K bytes
Up to 4K bytes can be on-chip (internal) of 8051 core
PSEN (Program Store Enable) is used for access to external Program Memory
Memory Organization (2/3)
Data Memory
Includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions
There is also a number of Special Function Registers (SFRs)
Internal Data Memory contains four banks of eight registers and a special 32-byte long segment which is bit addressable by 8051 bit-instructions
External memory of maximum 64K bytes is accessible by “movx”
Interrupt Structure
The 8051 provides 4 interrupt sources
Two external interrupts
Two timer interrupts
Additional description follows in Operations chapter
Port Structures (1/3)
The 8051 contains four I/O ports
All four ports are bidirectional
Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an output driver and an input buffer
Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing external memory
Port Structures (2/3)
Accessing external memory works like this
Port 0 outputs the low byte of external memory address (which is time-multiplexed with the byte being written or read)
Port 2 outputs the high byte (only needed when the address is 16 bits wide)
Port Structures (3/3)
Port 3 pins are multifunctional
The alternate functions are activated with the 1 written in the corresponding bit in the port SFR
Read-Modify-Write Feature (1/2)
When reading a port some instructions read the latch and others read the pin
The instructions that read the latch rather than the pin are the ones that read a value (possibly change it), an then rewrite it to the latch are called “read-modify-write” instructions
Timer/Counters
The 8051 has two 16-bit Timer/Counter registers
Timer 0
Timer 1
Both can work either as timers or event counters
Both have four different operating modes from which to select (all modes are described in Operations chapter)
Instruction Set
Optimized for 8-bit control applications
Fast addressing modes for accessing internal RAM in order to facilitate byte operations on small data structures
Good for systems that require a lot of Boolean processing because of its extensive support for one-bit variables as a separate data type
Addressing Modes (1/3)
Direct Addressing
Operand is specified by an 8-bit address field in the instruction
This address mode is possible only for addressing internal Data RAM and SFRs
Indirect Addressing
The instruction specifies a register which contains the address of the operand
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer
The address register for 16-bit addresses can only be 16-bit “data pointer” register, DPTR
Both internal and external RAM can be indirectly addressed
Addressing Modes (2/3)
Register Instructions
Special instructions are used for accessing four register banks (containing R0 to R7)
This instructions have 3-bit register specification within the opcode
This way of accessing registers is much more efficient because of no need for the address byte
When such instruction is executed one of registers in selected ban is accessed
Register bank is selected by two bank select bits in PSW
Addressing Modes (3/3)
Register-Specific Instructions
These are instructions which are specific to a certain register and they don’t need an address byte (they always operate with the same register)
Immediate Constants
The value of a constant follows the opcode
MOV A, #10 – loads the Accumulator with the decimal number 10
Indexed Addressing
Only Program Memory can be accessed and it can be a read
Used for reading look-up tables in Program Memory and “case jump” instruction
[attachment=30690]
Introduction
MCS-51 family, originally designed by Intel in the 1980’s
Used in a large percentage of embedded systems
Includes several on-chip peripherals, like timers and counters
128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory
Features (1/2)
8-bit CPU optimized for control applications
Extensive Boolean processing (single-bit logic) capabilities
64K Program Memory address space
64K Data Memory address space
Up to 4K bytes of on-chip Program Memory
128 bytes of on-chip Data RAM
32 bi-directional and individually addressable I/O lines
Two 16-bit timer/counters
6-source/5-vector interrupt structure with two priority levels
Memory Organization (1/3)
Logical separation of program and data memory
Separate address spaces for Program (ROM) and Data (RAM) Memory
Allow Data Memory to be accessed by 8-bit addresses quickly and manipulated by 8-bit CPU
Program Memory
Only be read, not written to
The address space is 16-bit, so maximum of 64K bytes
Up to 4K bytes can be on-chip (internal) of 8051 core
PSEN (Program Store Enable) is used for access to external Program Memory
Memory Organization (2/3)
Data Memory
Includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions
There is also a number of Special Function Registers (SFRs)
Internal Data Memory contains four banks of eight registers and a special 32-byte long segment which is bit addressable by 8051 bit-instructions
External memory of maximum 64K bytes is accessible by “movx”
Interrupt Structure
The 8051 provides 4 interrupt sources
Two external interrupts
Two timer interrupts
Additional description follows in Operations chapter
Port Structures (1/3)
The 8051 contains four I/O ports
All four ports are bidirectional
Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an output driver and an input buffer
Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing external memory
Port Structures (2/3)
Accessing external memory works like this
Port 0 outputs the low byte of external memory address (which is time-multiplexed with the byte being written or read)
Port 2 outputs the high byte (only needed when the address is 16 bits wide)
Port Structures (3/3)
Port 3 pins are multifunctional
The alternate functions are activated with the 1 written in the corresponding bit in the port SFR
Read-Modify-Write Feature (1/2)
When reading a port some instructions read the latch and others read the pin
The instructions that read the latch rather than the pin are the ones that read a value (possibly change it), an then rewrite it to the latch are called “read-modify-write” instructions
Timer/Counters
The 8051 has two 16-bit Timer/Counter registers
Timer 0
Timer 1
Both can work either as timers or event counters
Both have four different operating modes from which to select (all modes are described in Operations chapter)
Instruction Set
Optimized for 8-bit control applications
Fast addressing modes for accessing internal RAM in order to facilitate byte operations on small data structures
Good for systems that require a lot of Boolean processing because of its extensive support for one-bit variables as a separate data type
Addressing Modes (1/3)
Direct Addressing
Operand is specified by an 8-bit address field in the instruction
This address mode is possible only for addressing internal Data RAM and SFRs
Indirect Addressing
The instruction specifies a register which contains the address of the operand
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer
The address register for 16-bit addresses can only be 16-bit “data pointer” register, DPTR
Both internal and external RAM can be indirectly addressed
Addressing Modes (2/3)
Register Instructions
Special instructions are used for accessing four register banks (containing R0 to R7)
This instructions have 3-bit register specification within the opcode
This way of accessing registers is much more efficient because of no need for the address byte
When such instruction is executed one of registers in selected ban is accessed
Register bank is selected by two bank select bits in PSW
Addressing Modes (3/3)
Register-Specific Instructions
These are instructions which are specific to a certain register and they don’t need an address byte (they always operate with the same register)
Immediate Constants
The value of a constant follows the opcode
MOV A, #10 – loads the Accumulator with the decimal number 10
Indexed Addressing
Only Program Memory can be accessed and it can be a read
Used for reading look-up tables in Program Memory and “case jump” instruction