09-08-2012, 11:30 AM
A Fault Coverage-Driven Partial Scan Chain Selection Technique
[attachment=30707]
Abstract
Scan based design is a very popular approach to sequential
circuit testing. Full scan designs often involve
significant hardware and performance overheads. Partial
scan design, with it’s low overhead, offers an alternative
to the f i l l scan design. The main problem
in partial scan design is minimizing the magnitude of
the set of flip-flops to be included in the scan chain.
In the past, many solutions to this problem have been
proposed. In this paper, we propose a fault coverage
driven solution to this problem. Unlike ezisting
techniques, our solution is targeted towards achieving
100% fault coverage while minimizing the set of flipflops
to be included in the scan chain.
Introduction
Scan based design is a popular solution to the difficult
problem of sequential circuit testing [l, 2, 31
because it reduces the problem to testing of combinational
logic. However, full scan designs often involve
significant hardware and performance overhead
[4]. Partial scan is the inclusion of a subset of the
flip-flops in the scan chain. It offers an alternative to
the full scan design philosophy while preserving the
advantages of high fault coverage and reduced performance/
area penalties.
Experimental results
The partial scan design technique described in this
paper was applied to a subset of the ISCAS’89 ADDENDUM
benchmark circuits. Random fault simulation
was performed, beginning with the circuits in
the reset state, by applying 32,768 random vectors.
The set of undetected faults obtained from the fault
simulation were the “hard to detect” faults
[attachment=30707]
Abstract
Scan based design is a very popular approach to sequential
circuit testing. Full scan designs often involve
significant hardware and performance overheads. Partial
scan design, with it’s low overhead, offers an alternative
to the f i l l scan design. The main problem
in partial scan design is minimizing the magnitude of
the set of flip-flops to be included in the scan chain.
In the past, many solutions to this problem have been
proposed. In this paper, we propose a fault coverage
driven solution to this problem. Unlike ezisting
techniques, our solution is targeted towards achieving
100% fault coverage while minimizing the set of flipflops
to be included in the scan chain.
Introduction
Scan based design is a popular solution to the difficult
problem of sequential circuit testing [l, 2, 31
because it reduces the problem to testing of combinational
logic. However, full scan designs often involve
significant hardware and performance overhead
[4]. Partial scan is the inclusion of a subset of the
flip-flops in the scan chain. It offers an alternative to
the full scan design philosophy while preserving the
advantages of high fault coverage and reduced performance/
area penalties.
Experimental results
The partial scan design technique described in this
paper was applied to a subset of the ISCAS’89 ADDENDUM
benchmark circuits. Random fault simulation
was performed, beginning with the circuits in
the reset state, by applying 32,768 random vectors.
The set of undetected faults obtained from the fault
simulation were the “hard to detect” faults