11-08-2012, 03:44 PM
ARITHMETIC LOGIC UNIT (ALU) and BOOTH’S MULTIPLIER FOR AMR7 MICROPROCESSOR
[attachment=31162]
ABSTRACT
There are three major designs mentioned in this paper. First, the arithmetic logic unit (ALU) is designed to support for every conditional instruction in 32-bits ARM7 microprocessor. Two major tasks of ALU are to generate the result for arithmetic/logic operations and to generate the conditional signals. The functionalities of ALU consist of move, pass, add, add carry, subtract, subtract carry, bit-wise OR, bit-wise AND, bit-wise XOR, and bit-wise AND NOT. The adder in ALU is implemented by using a Carry Select Adder. Second, the multiplier, which supports for multi-cycle multiply instruction in ARM7, is designed by using Booth’s algorithm. Finally, the voltage regulator is designed to meet some specifications (output voltage’s tolerance, output current’s delivering, and input’s polarity).
Introduction
The high-level block diagram of 32-bit ARM7 microprocessor is shown in Figure.1 below. This processor will support 11 instructions: Data Processing Transfer, Multiply, Single Data Swap, Single Data Transfer, Undefined, Block Data Transfer, Branch, Coproc Data Transfer, Coproc Data Operation, Coproc ResigterTransfer, and Software interrupt. Our task is to design and implement the ALU and the Multiplier module to chip level by using synthesis tool (Synopsys with 0.25, 3.3V technology). Others will design the rest of the processor
Description of Booth’s multiplier:
The multiplier module takes inputs A, B (32-bits), Enable and System clock (Sysclk). This module will give the least significant 32 bits of the product of two 32-bit operands, and Ready. Enable signal tells when multiplying begins, and Ready signal tells when multiplying ends. The result of a signed multiply and of an unsigned multiply of 32-bit operands differ only in the upper 32 bits, the low 32 bits of the signed or unsigned result are identical. So, they can use for both signed and unsigned multiplies.
Description of ALU:
The ALU is a combinational logic unit. It takes two inputs of 32 bits wide and performs Logic and Arithmetic’s operations. The logic and arithmetic are operated depending on the 5-bit Alu_Control signal. The logic operations involve bit-wise and, bit-wise or, and bit-wise xor. The Arithmetic’s operations involve add, add Carry_in, sub, sub Carry_in, move from coprocessor register, and pass data. There are two outputs from ALU: 32_bit output and 4-bit Flag_signals. The 32-bit Output is the result depending on the operation of Input1 and Input2. The 4-bit Flag_signals support every conditional instruction in ARM7. They are broken down as [N,Z,C,V]. N indicates if Output is negative. Z indicates if Output is equal to zero. C indicates if the operation has carry out (this is only the case of Arithmetic’s operation). V indicates if we have the overflow situation (again, this is only the case of Arithmetic’s operation).
DESIGN PROCEDURE
Booth’s Multiplier
There are several algorithms to implement the multiplier. In ARM7, they choose Booth’s algorithm to implement the multiplier. This choice is desirable because Booth’s algorithm is simple to design. The alternative approach to this design is that we can implement the parallel multiplier or the Wallace Tree multiplier to gain better performance. However, these designs are much more complex.
We divide the design process into several steps:
First step: Draw the ASM (Algorithm State Machine) based on Booth’s algorithm, which is considered as the major design algorithm for the multiplier. The ASM of the multiplier is shown in Figure 1.3.
Second step: Based on the ASM, we write the behavioral Verilog code for the multiplier. Then we run the simulation to see if the multiplier performs its function correctly.
Third step: After verifying that the functionality of the multiplier works correctly, we begin to work on the architecture of the multiplier (actual hardware components used in the algorithm). Then, we write the mixed Verilog code for the multiplier (the combination of behavior and actual hardware for the multiplier). As always, we have to run the simulation to check if the mixed Verilog code agrees with the behavior code we wrote earlier.
Final step: In this step, the actual components are used to build the whole design. There is no behavior code involved. All the codes we wrote are called Structural-Code, which describes the design structurally. Again, we have to verify if the structural code gives the same result as the behavior and mixed code do. Once this is done, we use Synopsys to synthesize the structural code to get the real circuit, which is ready to fabricate at the chip level.
Arithmetic Logic Unit (ALU)
As the same with Multiplier above, we have to go through all the steps except the mixed stage. This is because of ALU, which is a combinational logic circuit. The combinational logic circuit does not need to have the mixed stage. We can go directly from the behavior code to the structural code and synthesize from here. The alternative approach to the design is that we can use a conditional – sum adder or a binary look ahead carry adder for better performance instead of the carry select adder. However, these designs will require a lot more complex.
CONCLUSION
We feel confident that our design works properly. Furthermore, we have met the specifications as stated in the introduction. The design of Booth’s multiplier runs at 455MHz with 0.25, 3.3V technology. However, we need to consider a faster speed for future design by shifting 2 bits per cycle instead of shifting 1 bit per cycle. The area of ALU is optimized to smallest area generated by Synopsys. There are different values of resistor we can choose from the equation (1) in order to design voltage regulator. However, we have chosen the values such that we have low power dissipation, which increases the reliability of the product.
[attachment=31162]
ABSTRACT
There are three major designs mentioned in this paper. First, the arithmetic logic unit (ALU) is designed to support for every conditional instruction in 32-bits ARM7 microprocessor. Two major tasks of ALU are to generate the result for arithmetic/logic operations and to generate the conditional signals. The functionalities of ALU consist of move, pass, add, add carry, subtract, subtract carry, bit-wise OR, bit-wise AND, bit-wise XOR, and bit-wise AND NOT. The adder in ALU is implemented by using a Carry Select Adder. Second, the multiplier, which supports for multi-cycle multiply instruction in ARM7, is designed by using Booth’s algorithm. Finally, the voltage regulator is designed to meet some specifications (output voltage’s tolerance, output current’s delivering, and input’s polarity).
Introduction
The high-level block diagram of 32-bit ARM7 microprocessor is shown in Figure.1 below. This processor will support 11 instructions: Data Processing Transfer, Multiply, Single Data Swap, Single Data Transfer, Undefined, Block Data Transfer, Branch, Coproc Data Transfer, Coproc Data Operation, Coproc ResigterTransfer, and Software interrupt. Our task is to design and implement the ALU and the Multiplier module to chip level by using synthesis tool (Synopsys with 0.25, 3.3V technology). Others will design the rest of the processor
Description of Booth’s multiplier:
The multiplier module takes inputs A, B (32-bits), Enable and System clock (Sysclk). This module will give the least significant 32 bits of the product of two 32-bit operands, and Ready. Enable signal tells when multiplying begins, and Ready signal tells when multiplying ends. The result of a signed multiply and of an unsigned multiply of 32-bit operands differ only in the upper 32 bits, the low 32 bits of the signed or unsigned result are identical. So, they can use for both signed and unsigned multiplies.
Description of ALU:
The ALU is a combinational logic unit. It takes two inputs of 32 bits wide and performs Logic and Arithmetic’s operations. The logic and arithmetic are operated depending on the 5-bit Alu_Control signal. The logic operations involve bit-wise and, bit-wise or, and bit-wise xor. The Arithmetic’s operations involve add, add Carry_in, sub, sub Carry_in, move from coprocessor register, and pass data. There are two outputs from ALU: 32_bit output and 4-bit Flag_signals. The 32-bit Output is the result depending on the operation of Input1 and Input2. The 4-bit Flag_signals support every conditional instruction in ARM7. They are broken down as [N,Z,C,V]. N indicates if Output is negative. Z indicates if Output is equal to zero. C indicates if the operation has carry out (this is only the case of Arithmetic’s operation). V indicates if we have the overflow situation (again, this is only the case of Arithmetic’s operation).
DESIGN PROCEDURE
Booth’s Multiplier
There are several algorithms to implement the multiplier. In ARM7, they choose Booth’s algorithm to implement the multiplier. This choice is desirable because Booth’s algorithm is simple to design. The alternative approach to this design is that we can implement the parallel multiplier or the Wallace Tree multiplier to gain better performance. However, these designs are much more complex.
We divide the design process into several steps:
First step: Draw the ASM (Algorithm State Machine) based on Booth’s algorithm, which is considered as the major design algorithm for the multiplier. The ASM of the multiplier is shown in Figure 1.3.
Second step: Based on the ASM, we write the behavioral Verilog code for the multiplier. Then we run the simulation to see if the multiplier performs its function correctly.
Third step: After verifying that the functionality of the multiplier works correctly, we begin to work on the architecture of the multiplier (actual hardware components used in the algorithm). Then, we write the mixed Verilog code for the multiplier (the combination of behavior and actual hardware for the multiplier). As always, we have to run the simulation to check if the mixed Verilog code agrees with the behavior code we wrote earlier.
Final step: In this step, the actual components are used to build the whole design. There is no behavior code involved. All the codes we wrote are called Structural-Code, which describes the design structurally. Again, we have to verify if the structural code gives the same result as the behavior and mixed code do. Once this is done, we use Synopsys to synthesize the structural code to get the real circuit, which is ready to fabricate at the chip level.
Arithmetic Logic Unit (ALU)
As the same with Multiplier above, we have to go through all the steps except the mixed stage. This is because of ALU, which is a combinational logic circuit. The combinational logic circuit does not need to have the mixed stage. We can go directly from the behavior code to the structural code and synthesize from here. The alternative approach to the design is that we can use a conditional – sum adder or a binary look ahead carry adder for better performance instead of the carry select adder. However, these designs will require a lot more complex.
CONCLUSION
We feel confident that our design works properly. Furthermore, we have met the specifications as stated in the introduction. The design of Booth’s multiplier runs at 455MHz with 0.25, 3.3V technology. However, we need to consider a faster speed for future design by shifting 2 bits per cycle instead of shifting 1 bit per cycle. The area of ALU is optimized to smallest area generated by Synopsys. There are different values of resistor we can choose from the equation (1) in order to design voltage regulator. However, we have chosen the values such that we have low power dissipation, which increases the reliability of the product.