16-08-2012, 02:25 PM
Design of AHB Protocol Block for Advanced Microcontrollers
[attachment=31676]
ABSTRACT
The AMBA Advanced high performance bus (AHB) protocol design acts as an interface between two different IP cores. In this work initially the investigation on the AHB is carried out and the basic commands and its working are identified based on which the signal flow diagram and the specifications are developed for designing the AMBA-AHB using VHDL. In this paper we propose the design and implementation of a flexible arbiter scheme for the AHB busmatrix based on burst operation. Basically, AHB burst operation is that a sequence of operation happens with respect to the size given and it supports only three burst sizes. The size is acting as one of the input to the master during the burst operation and after each burst operation, the master or slave will go to the IDLE stage. The AHB design contains basic blocks such as master and slave and the working of these blocks based on arbitration scheme. According to arbitration scheme only one master can Access the bus at any one time. Multiplexer and Decoders are used to selects the appropriate signals between master and slaves that are involved in the transfer. This AMBA-AHB protocol can be adopted in all the applications provided the design should be an AHB compliant.
INTRODUCTION
In recent days , the development of SOC chips and the reusable IP cores are given higher priority because of its less cost and reduction in the period of Time-to-market . So this enables the major and very sensitive issue such as interfacing of these IP cores. These interfaces play a vital role in SOC and should be taken care because of the communication between the IP cores property.
The on chip bus used in the SOC design by enabling the efficient integration of heterogeneous system components such as CPUS , DSPS , Application specific cores, Memories and custom logic. The SOC design requires a system bus with high bandwidth to perform multiple operations in parallel. To solve the bandwidth problems, there have been several types of high performance on chip buses proposed
MICROCONTROLLER STRUCTURE BASED ON AMBA-AHB
This type of microcontroller structure consists High perform- -ance ARM processor , High bandwidth on chip RAM, High bandwidth external memory ,Direct memory access (DMA) device, Bridge as a converter ,UART ,Timer, Keypad , PIO and other devices based on application as shown in fig 2.1. An AMBA based microcontroller typically consists a high performance system backbone bus (AMBA-AHB), able to sustain the external memory bandwidth, on which the above given devices reside. This bus provides a high bandwidth interface between the elements that are involved in the majority of transfers. Also located on the high performance bus is a bridge to the lower bandwidth APB, where most of the peripheral devices in the system are located.
DESIGN OF AMBA-AHB WITH FSM
The literature survey on the AHB is made and the basic signal flow block diagram is identified. In the data flow signal diagram the basic signals are used in the simple read write and burst operation in AHB master and slave. Finite state machine (FSM) is developed and then modeled using VHDL.
CONCLUSION
1 From the AMBA-AHB design we conclude that minimum period used in the design is 57.142ns and maximum frequency is 17.500MHz which is comparatively good result. The AHB is designed in such a way that the transaction between master and slave is carried out with proper delay and timings. We could design the intellectual properties of the master and slave depending upon specifications, data transfer and various transfer modes that are supported by AMBA bus architecture. Depending upon the real time application these intellectual properties can be used for designing high performance embedded microcontroller.
2 The various scenarios for each component in the AMBA-AHB bus design are verified effectively during the simulation with respect to its behavior.
[attachment=31676]
ABSTRACT
The AMBA Advanced high performance bus (AHB) protocol design acts as an interface between two different IP cores. In this work initially the investigation on the AHB is carried out and the basic commands and its working are identified based on which the signal flow diagram and the specifications are developed for designing the AMBA-AHB using VHDL. In this paper we propose the design and implementation of a flexible arbiter scheme for the AHB busmatrix based on burst operation. Basically, AHB burst operation is that a sequence of operation happens with respect to the size given and it supports only three burst sizes. The size is acting as one of the input to the master during the burst operation and after each burst operation, the master or slave will go to the IDLE stage. The AHB design contains basic blocks such as master and slave and the working of these blocks based on arbitration scheme. According to arbitration scheme only one master can Access the bus at any one time. Multiplexer and Decoders are used to selects the appropriate signals between master and slaves that are involved in the transfer. This AMBA-AHB protocol can be adopted in all the applications provided the design should be an AHB compliant.
INTRODUCTION
In recent days , the development of SOC chips and the reusable IP cores are given higher priority because of its less cost and reduction in the period of Time-to-market . So this enables the major and very sensitive issue such as interfacing of these IP cores. These interfaces play a vital role in SOC and should be taken care because of the communication between the IP cores property.
The on chip bus used in the SOC design by enabling the efficient integration of heterogeneous system components such as CPUS , DSPS , Application specific cores, Memories and custom logic. The SOC design requires a system bus with high bandwidth to perform multiple operations in parallel. To solve the bandwidth problems, there have been several types of high performance on chip buses proposed
MICROCONTROLLER STRUCTURE BASED ON AMBA-AHB
This type of microcontroller structure consists High perform- -ance ARM processor , High bandwidth on chip RAM, High bandwidth external memory ,Direct memory access (DMA) device, Bridge as a converter ,UART ,Timer, Keypad , PIO and other devices based on application as shown in fig 2.1. An AMBA based microcontroller typically consists a high performance system backbone bus (AMBA-AHB), able to sustain the external memory bandwidth, on which the above given devices reside. This bus provides a high bandwidth interface between the elements that are involved in the majority of transfers. Also located on the high performance bus is a bridge to the lower bandwidth APB, where most of the peripheral devices in the system are located.
DESIGN OF AMBA-AHB WITH FSM
The literature survey on the AHB is made and the basic signal flow block diagram is identified. In the data flow signal diagram the basic signals are used in the simple read write and burst operation in AHB master and slave. Finite state machine (FSM) is developed and then modeled using VHDL.
CONCLUSION
1 From the AMBA-AHB design we conclude that minimum period used in the design is 57.142ns and maximum frequency is 17.500MHz which is comparatively good result. The AHB is designed in such a way that the transaction between master and slave is carried out with proper delay and timings. We could design the intellectual properties of the master and slave depending upon specifications, data transfer and various transfer modes that are supported by AMBA bus architecture. Depending upon the real time application these intellectual properties can be used for designing high performance embedded microcontroller.
2 The various scenarios for each component in the AMBA-AHB bus design are verified effectively during the simulation with respect to its behavior.