17-08-2012, 02:50 PM
Designing a scalable OFDMA engine for WiMAX
[attachment=31868]
WiMAX is fast gaining traction
in the competitive world
of broadband wireless access
technology with many analysts
acknowledging that it has significant
market potential.
Scalable orthogonal frequency-
division multiple access
(OFDMA) is a key technology
behind mobile WiMAX—as it is
with other wireless technologies.
OFDMA is also expected to play
a key role 3GPP and 3GPP2 long
term evolution standards.
To achieve competitive systems,
however, designers and
OEMs must choose a silicon
platform that offers flexibility,
scalability and a risk-free costreduction
path. This is particularly
true of an OFDMA engine
because of its high performance
requirements.
WiMAX PHY layer system
design
WiMAX is gaining popularity as a
broadband wireless access technology
with significant market
potential. To achieve competitive
systems it is necessary to choose
a silicon platform that offers flexibility,
scalability and a risk-free
cost-reduction path.
A comprehensive wireless
ecosystem portfolio offers a
broad family of FPGA devices,
intellectual property (IP), reference
designs, development
boards and WiMAX-compliant,
off-the-shelf channel and RF
card solutions through partners.
By leveraging these offerings
and partners, WiMAX OEMs can
accelerate their own internal
make solution or buy a complete
off-the-shelf solution and get to
market faster utilizing FPGAbased
WiMAX designs.
OFDM Kernel
The OFDM kernel handles the
FFT operations and cyclic prefix
addition and removal. The FFT
size is a parameter that must be
specified at synthesis time, but
can change the guard interval
at run time. Downlink transmit
The downlink OFDM kernel module
performs an inverse Fourier
transform of the frequency
domain input data and adds a
cyclic prefix to the resulting time
domain data.
The cyclic prefix addition
block contains a controller that
buffers the output packets from
the FFT, and adds the appropriate
proportion of the end of the
output packet to the beginning
of the output packet.
Since this requires a fairly significant
memory resource, the
hardware architecture has been
designed so that the embedded
memory may be shared with the
uplink OFDM kernel if the modem
is operating in time division
duplex (TDD) mode.
[attachment=31868]
WiMAX is fast gaining traction
in the competitive world
of broadband wireless access
technology with many analysts
acknowledging that it has significant
market potential.
Scalable orthogonal frequency-
division multiple access
(OFDMA) is a key technology
behind mobile WiMAX—as it is
with other wireless technologies.
OFDMA is also expected to play
a key role 3GPP and 3GPP2 long
term evolution standards.
To achieve competitive systems,
however, designers and
OEMs must choose a silicon
platform that offers flexibility,
scalability and a risk-free costreduction
path. This is particularly
true of an OFDMA engine
because of its high performance
requirements.
WiMAX PHY layer system
design
WiMAX is gaining popularity as a
broadband wireless access technology
with significant market
potential. To achieve competitive
systems it is necessary to choose
a silicon platform that offers flexibility,
scalability and a risk-free
cost-reduction path.
A comprehensive wireless
ecosystem portfolio offers a
broad family of FPGA devices,
intellectual property (IP), reference
designs, development
boards and WiMAX-compliant,
off-the-shelf channel and RF
card solutions through partners.
By leveraging these offerings
and partners, WiMAX OEMs can
accelerate their own internal
make solution or buy a complete
off-the-shelf solution and get to
market faster utilizing FPGAbased
WiMAX designs.
OFDM Kernel
The OFDM kernel handles the
FFT operations and cyclic prefix
addition and removal. The FFT
size is a parameter that must be
specified at synthesis time, but
can change the guard interval
at run time. Downlink transmit
The downlink OFDM kernel module
performs an inverse Fourier
transform of the frequency
domain input data and adds a
cyclic prefix to the resulting time
domain data.
The cyclic prefix addition
block contains a controller that
buffers the output packets from
the FFT, and adds the appropriate
proportion of the end of the
output packet to the beginning
of the output packet.
Since this requires a fairly significant
memory resource, the
hardware architecture has been
designed so that the embedded
memory may be shared with the
uplink OFDM kernel if the modem
is operating in time division
duplex (TDD) mode.