23-08-2012, 02:50 PM
16-Bit, 2.5MSPS Analog-to-Digital Converter
[attachment=32519]
DESCRIPTION
The ADS1602 is a high-speed, high-precision,
delta-sigma analog-to-digital converter (ADC)
manufactured on an advanced CMOS process. The
ADS1602 oversampling topology reduces clock jitter
sensitivity during the sampling of high-frequency, large
amplitude signals by a factor of four over that achieved by
Nyquist-rate ADCs. Consequently, signal-to-noise ratio
(SNR) is particularly improved. Total harmonic distortion
(THD) is −101dB, and the spurious-free dynamic range
(SFDR) is 103dB.
Optimized for power and performance, the ADS1602
dissipates only 530mW while providing a full-scale
differential input range of ±3V. Having such a wide input
range makes out-of-range signals unlikely. The OTR pin
indicates if an analog input out-of-range condition does
occur. The differential input signal is measured against the
differential reference, which can be generated internally or
supplied externally on the ADS1602.
The ADS1602 uses an inherently stable advanced
modulator with an on-chip decimation filter. The filter stop
band extends to 38.6MHz, which greatly simplifies the
anti-aliasing circuitry. The modulator samples the input
signal up to 40MSPS, depending on fCLK, while the 16x
decimation filter uses a series of four half-band FIR filter
stages to provide 75dB of stop band attenuation and
0.001dB of passband ripple.
OVERVIEW
The ADS1602 is a high-performance delta-sigma ADC.
The modulator uses an inherently stable 2-1-1 multi-stage
architecture incorporating proprietary circuitry that allows
for very linear high-speed operation. The modulator
samples the input signal at 40MSPS (when fCLK = 40MHz).
A low-ripple linear phase digital filter decimates the
modulator output by 16 to provide high resolution 16-bit
output data.
Conceptually, the modulator and digital filter measure the
differential input signal, VIN = (AINP – AINN), against the
scaled differential reference, VREF = (VREFP – VREFN),
as shown in Figure 38. The voltage reference can either be
generated internally or supplied externally. A 3-wire serial
interface, designed for direct connection to DSPs, outputs
the data. A separate power supply for the I/O allows flexibility
for interfacing to different logic families. Out-of-range
conditions are indicated with a dedicated digital output pin.
Analog power dissipation is controlled using an external
resistor. This control allows reduced dissipation when operating
at slower speeds. When not in use, power consumption
can be dramatically reduced by setting the PD
pin low to enter Power-Down mode.
INPUT CIRCUITRY
The ADS1602 uses switched-capacitor circuitry to measure
the input voltage. Internal capacitors are charged by the
inputs and then discharged internally with this cycle
repeating at the frequency of CLK. Figure 39 shows a
conceptual diagram of these circuits. Switches S2 represent
the net effect of the modulator circuitry in discharging the
sampling capacitors; the actual implementation is different.
The timing for switches S1 and S2 is shown in Figure 40.
LAYOUT ISSUES AND COMPONENT SELECTION
The ADS1602 is a very high-speed, high-resolution data
converter. In order to achieve maximum performance, the
user must give very careful consideration to both the layout
of the printed circuit board (PCB) in addition to the routing
of the traces. Capacitors that are critical to achieve the
best performance from the device should be placed as
close to the pins of the device as possible. These include
capacitors related the analog inputs, the reference and the
power supplies.
For critical capacitors, it is recommended that Class II
dielectrics such as Z5U be avoided. These dielectrics
have a narrow operating temperature, a large tolerance on
the capacitance and will lose up to 20% of the rated
capacitance over 10,000 hours. Rather, select capacitors
with a Class I dielectric. C0G (also known as NP0), for
example, has a tight tolerance < ±30PPM/°C and is very
stable over time. Should Class II capacitors be chosen
because of the size constraints, select an X7R or X5R
dielectric to minimize the variations of the capacitor’s
critical characteristics.
[attachment=32519]
DESCRIPTION
The ADS1602 is a high-speed, high-precision,
delta-sigma analog-to-digital converter (ADC)
manufactured on an advanced CMOS process. The
ADS1602 oversampling topology reduces clock jitter
sensitivity during the sampling of high-frequency, large
amplitude signals by a factor of four over that achieved by
Nyquist-rate ADCs. Consequently, signal-to-noise ratio
(SNR) is particularly improved. Total harmonic distortion
(THD) is −101dB, and the spurious-free dynamic range
(SFDR) is 103dB.
Optimized for power and performance, the ADS1602
dissipates only 530mW while providing a full-scale
differential input range of ±3V. Having such a wide input
range makes out-of-range signals unlikely. The OTR pin
indicates if an analog input out-of-range condition does
occur. The differential input signal is measured against the
differential reference, which can be generated internally or
supplied externally on the ADS1602.
The ADS1602 uses an inherently stable advanced
modulator with an on-chip decimation filter. The filter stop
band extends to 38.6MHz, which greatly simplifies the
anti-aliasing circuitry. The modulator samples the input
signal up to 40MSPS, depending on fCLK, while the 16x
decimation filter uses a series of four half-band FIR filter
stages to provide 75dB of stop band attenuation and
0.001dB of passband ripple.
OVERVIEW
The ADS1602 is a high-performance delta-sigma ADC.
The modulator uses an inherently stable 2-1-1 multi-stage
architecture incorporating proprietary circuitry that allows
for very linear high-speed operation. The modulator
samples the input signal at 40MSPS (when fCLK = 40MHz).
A low-ripple linear phase digital filter decimates the
modulator output by 16 to provide high resolution 16-bit
output data.
Conceptually, the modulator and digital filter measure the
differential input signal, VIN = (AINP – AINN), against the
scaled differential reference, VREF = (VREFP – VREFN),
as shown in Figure 38. The voltage reference can either be
generated internally or supplied externally. A 3-wire serial
interface, designed for direct connection to DSPs, outputs
the data. A separate power supply for the I/O allows flexibility
for interfacing to different logic families. Out-of-range
conditions are indicated with a dedicated digital output pin.
Analog power dissipation is controlled using an external
resistor. This control allows reduced dissipation when operating
at slower speeds. When not in use, power consumption
can be dramatically reduced by setting the PD
pin low to enter Power-Down mode.
INPUT CIRCUITRY
The ADS1602 uses switched-capacitor circuitry to measure
the input voltage. Internal capacitors are charged by the
inputs and then discharged internally with this cycle
repeating at the frequency of CLK. Figure 39 shows a
conceptual diagram of these circuits. Switches S2 represent
the net effect of the modulator circuitry in discharging the
sampling capacitors; the actual implementation is different.
The timing for switches S1 and S2 is shown in Figure 40.
LAYOUT ISSUES AND COMPONENT SELECTION
The ADS1602 is a very high-speed, high-resolution data
converter. In order to achieve maximum performance, the
user must give very careful consideration to both the layout
of the printed circuit board (PCB) in addition to the routing
of the traces. Capacitors that are critical to achieve the
best performance from the device should be placed as
close to the pins of the device as possible. These include
capacitors related the analog inputs, the reference and the
power supplies.
For critical capacitors, it is recommended that Class II
dielectrics such as Z5U be avoided. These dielectrics
have a narrow operating temperature, a large tolerance on
the capacitance and will lose up to 20% of the rated
capacitance over 10,000 hours. Rather, select capacitors
with a Class I dielectric. C0G (also known as NP0), for
example, has a tight tolerance < ±30PPM/°C and is very
stable over time. Should Class II capacitors be chosen
because of the size constraints, select an X7R or X5R
dielectric to minimize the variations of the capacitor’s
critical characteristics.