31-08-2012, 11:56 AM
Asynchronous Microprocessors
[attachment=32986]
INTRODUCTION
We all know about the synchronous and asynchronous systems. Based on this microprocessors can be categorised as synchronous and asynchronous microprocessors. Most of the existing processor used today is synchronous processors. In a synchronous system, operations are coordinated under the centralized control of a fixed-rate clock signal or several clocks. An asynchronous digital system, in contrast, has no global clock: instead, it operates under distributed control, with concurrent hardware components communicating and synchronizing on channels. Due to ever increasing need for faster systems, asynchronous systems have become a viable alternative. This paper describes the various steps to design asynchronous microprocessors and its various features.
With progress of time and improvement of technology, clocks get faster, the chips have higher circuit density and the wires get finer. As a result, it becomes increasingly difficult to ensure that all parts of the processor are ticking along in step with each other. Even though the electrical clock pulses are travelling at a substantial fraction of the speed of light, the delays in getting from one side of a small piece of silicon to the other can be enough to throw the chip's operation out of synchronization. Even if the clock were injected optically to avoid the wire delays, the signals issued as a result of the clock would still have to propagate along wires in time for the next clock pulse, and similar problem would remain. This clock related timing problems are recently attacked by asynchronous (or self-timed) design techniques. These asynchronous processors do away with the idea of having a single central clock keeping the chip’s functional units in step.
LITERATURE SURVEY
Before the evolution of asynchronous processors, the synchronous processors plays the important role, and after the asynchronous processors come into a breaking step, several asynchronous logics are evolved at the first stage before the evolution of AMULET chips. In this chapter there is a small description given about the papers presented by some people as a logic step to the evolution of asynchronous microprocessors and AMULET.
In 1981, Benincasa, G. P.; Giudici, F.; Skarek, P, presented a paper about the topic “Fast Synchronous Beam Property Modulation Using a Large Distributed Microprocessor System”[1],which describes the use and advantage of synchronous microprocessors. This task is handled by 20 microprocessor-based Auxiliary CAMAC Crate Controllers (ACC). This layout offers three major possibilities: (i) fast and reliable parameter refreshment in each cycle; (ii) the microprocessors constitute a distributed database, which allows autonomous execution of complicated tasks triggered by simple commands from the process computer; (iii) the microprocessors allow complete decoupling between the severe process real-time constraints and human interaction: asynchronous operator commands are executed in a precise synchronous way with the process.
HISTORY OF ASYNCHRONOUS MICROPROCESSORS
Virtually all digital is based on a synchronous approach. In synchronous logic, a system consists of the composition of one or more subsystems, each of which is a clocked finite-state machine; the subsystem changes from one state to the next on the edges of a regular clock The state is held in a set of flip-flops (registers), and combinatorial logic is used to derive the new state and outputs from the old state and inputs. The new state is copied through the flip-flops on every rising edge of the clock signal.
Special techniques are required whenever a signal enters the domain of a particular clock (either from outside the system or from the domain of a different clock within the same system), but otherwise the system behaves in a discrete and deterministic way provided that a few rules are followed. These rules include managing the delays of the combinatorial logic so that the flip flop setup and hold times are always met. However, there is an alternative approach that omits all this complication. In asynchronous design, in general & there is no clock to govern the timing of state changes. Subsystems exchange information at mutually negotiated times with no external timing regulation.
The chip’s clock is an oscillating crystal that vibrates at a regular frequency, depending on the voltage applied. This frequency is measured in gigahertz or megahertz. All the chips work is synchronized via the clock, which sends its signals out along all circuits and controls the registers, the data flow, and the order in which the processor performs the necessary tasks. An advantage of synchronous chips is that the order in which signals arrive doesn’t matter. Signals can arrive at different times, but the register waits until the next clock tick before capturing them. As long as they all arrive before the next tick, the system can process them in the proper order. Designers thus don’t have to worry about related issues, such as wire lengths, when working on chips. And it is easier to determine the maximum performance of a clocked system. With these systems, calculating performance simply involves counting the number of clock cycles needed to complete an operation. Calculating performance is less defined with asynchronous designs. This is an important marketing consideration.
CALTECH ASYNCHRONOUS MICROPROCESSOR
The CAM is a 16-bit RISC with 16 general-purpose registers, four buses, an ALU, two adders, and separate instruction and data memories. Because of the processor’s compact design, a five-person team moved from specification to tape-out in five months.
The CAM’s circuits belong to the traditional QDI logic family. The basis of this logic family is a buffer that inputs a value x on one channel (say, L) and outputs the computation result f(x) on another channel (say,R). The CHP expression for this buffer is *[L?x; R!f (x)].
The buffer can have several inputs and outputs including conditional ones. For simplicity, assume f is the identity function. Then, we obtain the HSE for the buffer by replacing L?x and
R!x with their HSEs.
To facilitate the decomposition, we use different HSEs for send and receive from those we presented earlier. Rather than an acknowledge signal, the handshake now uses a request signal: L.r for the receive HSE and R.r for the send HSE.
LUTONIUM 8051 MICROCONTROLLER
The latest project is the Lutonium, a QDI asynchronous 8051-architecture microcontroller designed for energy efficiency. Although the 8051’s complex instruction set and irregular use of registers do not make it an obvious candidate for an energy-efficient design, it is the most popular microcontroller and hence is often used in applications where low energy consumption is important. The 8051 microcontroller has 255 variable-length instructions, each 1 to 3 bytes long. The opcode is encoded in the instruction’s first byte, and the operands, if any, are stored in the second and third bytes. Instruction and data memories are separate. The 8051 peripherals include logic ports, timers and counters, I/O ports, and an interrupt controller. We chose an ambitious, highly concurrent design for the Lutonium. Most
instructions run in a single cycle. Standard 8051implementations share a single, global bus for many different operations. For energy efficiency, our pipelined design instead uses point-to-point channels that can operate concurrently. Other new energy-efficient features include a deep sleep mechanism with instant wake-up.
ASYNCHRONOUS DESIGN TECHNIQUES
The growth in demand for high performance portable computing equipment has led to a resurgence of interest in asynchronous logic design techniques. In order to investigate the power saving potential of asynchronous approaches to CMOS design a self-timed implementation of the ARM microprocessor has been developed as a commercially realistic technology demonstrator. The methodology applied to the design was based on Sutherland’s “Micropipelines”, a bundled-data, bounded-delay model. Here, local timing signals are transmitted with a ‘bundle’ of data bits whose timing is constrained to ensure correct operation. This technique was chosen for its economy in silicon area and its potential for low electrical power consumption.
The introduction of RISC instruction sets in the early1980s traded instruction semantic content for pipelined operation and RISC microprocessors have led the race for higher performance ever Since. More recently, power-efficiency (measured in units such as MIPS per watt) has become as important as performance for significant application areas and processor designers have begun to turn their attention to power saving techniques. One aspect of current microprocessor design practice which adversely affects power efficiency is the use of a high-speed clock to control the operation of the pipeline. This clock forces the inclusion of large sections of logic which are normally redundant but which are required to ensure that rare worst cases complete within the clock cycle time. The clock also causes power to be dissipated in all the systems on a chip, whether or not they are performing a useful function at the time. Modern power-sensitive design attempts to reduce this wastage by gating the clocks to independent function units so that they can be turned off when not needed.
ASYNCHRONOUS DESIGN
Asynchronous design, whilst offering the potential advantages for power-saving outlined above, also introduces a number of new difficulties: where independent function units wish to cornmunicate information, synchronization must be explicit; when independent units share a common resource in a non-deterministic fashion, arbiters capable of handling metastability reliably must be system must be free from dead lock (and live lock).The approach taken on AMULET1 is based on Sutherland's micropipeline. Here all activity is data driven: a new data value arrives at a function unit in normal binary encoding on a bus; its presence then signalled to the unit by a transition on the Request wire. This transition causes the unit to accept that data, signalling the acceptance by making a transition on the Acknowledge Wire. The data can then change to its next value. The request-acknowledge signalling supports full flow control at every communication interface in the design. Sutherland proposed a special form of 'capture-pass' latch for use in micro pipelines which requires 24 transistors per bit. A revised form of this latch is illustrated in figure (3) where the transistor count has been reduced to 18 per bit.
[attachment=32986]
INTRODUCTION
We all know about the synchronous and asynchronous systems. Based on this microprocessors can be categorised as synchronous and asynchronous microprocessors. Most of the existing processor used today is synchronous processors. In a synchronous system, operations are coordinated under the centralized control of a fixed-rate clock signal or several clocks. An asynchronous digital system, in contrast, has no global clock: instead, it operates under distributed control, with concurrent hardware components communicating and synchronizing on channels. Due to ever increasing need for faster systems, asynchronous systems have become a viable alternative. This paper describes the various steps to design asynchronous microprocessors and its various features.
With progress of time and improvement of technology, clocks get faster, the chips have higher circuit density and the wires get finer. As a result, it becomes increasingly difficult to ensure that all parts of the processor are ticking along in step with each other. Even though the electrical clock pulses are travelling at a substantial fraction of the speed of light, the delays in getting from one side of a small piece of silicon to the other can be enough to throw the chip's operation out of synchronization. Even if the clock were injected optically to avoid the wire delays, the signals issued as a result of the clock would still have to propagate along wires in time for the next clock pulse, and similar problem would remain. This clock related timing problems are recently attacked by asynchronous (or self-timed) design techniques. These asynchronous processors do away with the idea of having a single central clock keeping the chip’s functional units in step.
LITERATURE SURVEY
Before the evolution of asynchronous processors, the synchronous processors plays the important role, and after the asynchronous processors come into a breaking step, several asynchronous logics are evolved at the first stage before the evolution of AMULET chips. In this chapter there is a small description given about the papers presented by some people as a logic step to the evolution of asynchronous microprocessors and AMULET.
In 1981, Benincasa, G. P.; Giudici, F.; Skarek, P, presented a paper about the topic “Fast Synchronous Beam Property Modulation Using a Large Distributed Microprocessor System”[1],which describes the use and advantage of synchronous microprocessors. This task is handled by 20 microprocessor-based Auxiliary CAMAC Crate Controllers (ACC). This layout offers three major possibilities: (i) fast and reliable parameter refreshment in each cycle; (ii) the microprocessors constitute a distributed database, which allows autonomous execution of complicated tasks triggered by simple commands from the process computer; (iii) the microprocessors allow complete decoupling between the severe process real-time constraints and human interaction: asynchronous operator commands are executed in a precise synchronous way with the process.
HISTORY OF ASYNCHRONOUS MICROPROCESSORS
Virtually all digital is based on a synchronous approach. In synchronous logic, a system consists of the composition of one or more subsystems, each of which is a clocked finite-state machine; the subsystem changes from one state to the next on the edges of a regular clock The state is held in a set of flip-flops (registers), and combinatorial logic is used to derive the new state and outputs from the old state and inputs. The new state is copied through the flip-flops on every rising edge of the clock signal.
Special techniques are required whenever a signal enters the domain of a particular clock (either from outside the system or from the domain of a different clock within the same system), but otherwise the system behaves in a discrete and deterministic way provided that a few rules are followed. These rules include managing the delays of the combinatorial logic so that the flip flop setup and hold times are always met. However, there is an alternative approach that omits all this complication. In asynchronous design, in general & there is no clock to govern the timing of state changes. Subsystems exchange information at mutually negotiated times with no external timing regulation.
The chip’s clock is an oscillating crystal that vibrates at a regular frequency, depending on the voltage applied. This frequency is measured in gigahertz or megahertz. All the chips work is synchronized via the clock, which sends its signals out along all circuits and controls the registers, the data flow, and the order in which the processor performs the necessary tasks. An advantage of synchronous chips is that the order in which signals arrive doesn’t matter. Signals can arrive at different times, but the register waits until the next clock tick before capturing them. As long as they all arrive before the next tick, the system can process them in the proper order. Designers thus don’t have to worry about related issues, such as wire lengths, when working on chips. And it is easier to determine the maximum performance of a clocked system. With these systems, calculating performance simply involves counting the number of clock cycles needed to complete an operation. Calculating performance is less defined with asynchronous designs. This is an important marketing consideration.
CALTECH ASYNCHRONOUS MICROPROCESSOR
The CAM is a 16-bit RISC with 16 general-purpose registers, four buses, an ALU, two adders, and separate instruction and data memories. Because of the processor’s compact design, a five-person team moved from specification to tape-out in five months.
The CAM’s circuits belong to the traditional QDI logic family. The basis of this logic family is a buffer that inputs a value x on one channel (say, L) and outputs the computation result f(x) on another channel (say,R). The CHP expression for this buffer is *[L?x; R!f (x)].
The buffer can have several inputs and outputs including conditional ones. For simplicity, assume f is the identity function. Then, we obtain the HSE for the buffer by replacing L?x and
R!x with their HSEs.
To facilitate the decomposition, we use different HSEs for send and receive from those we presented earlier. Rather than an acknowledge signal, the handshake now uses a request signal: L.r for the receive HSE and R.r for the send HSE.
LUTONIUM 8051 MICROCONTROLLER
The latest project is the Lutonium, a QDI asynchronous 8051-architecture microcontroller designed for energy efficiency. Although the 8051’s complex instruction set and irregular use of registers do not make it an obvious candidate for an energy-efficient design, it is the most popular microcontroller and hence is often used in applications where low energy consumption is important. The 8051 microcontroller has 255 variable-length instructions, each 1 to 3 bytes long. The opcode is encoded in the instruction’s first byte, and the operands, if any, are stored in the second and third bytes. Instruction and data memories are separate. The 8051 peripherals include logic ports, timers and counters, I/O ports, and an interrupt controller. We chose an ambitious, highly concurrent design for the Lutonium. Most
instructions run in a single cycle. Standard 8051implementations share a single, global bus for many different operations. For energy efficiency, our pipelined design instead uses point-to-point channels that can operate concurrently. Other new energy-efficient features include a deep sleep mechanism with instant wake-up.
ASYNCHRONOUS DESIGN TECHNIQUES
The growth in demand for high performance portable computing equipment has led to a resurgence of interest in asynchronous logic design techniques. In order to investigate the power saving potential of asynchronous approaches to CMOS design a self-timed implementation of the ARM microprocessor has been developed as a commercially realistic technology demonstrator. The methodology applied to the design was based on Sutherland’s “Micropipelines”, a bundled-data, bounded-delay model. Here, local timing signals are transmitted with a ‘bundle’ of data bits whose timing is constrained to ensure correct operation. This technique was chosen for its economy in silicon area and its potential for low electrical power consumption.
The introduction of RISC instruction sets in the early1980s traded instruction semantic content for pipelined operation and RISC microprocessors have led the race for higher performance ever Since. More recently, power-efficiency (measured in units such as MIPS per watt) has become as important as performance for significant application areas and processor designers have begun to turn their attention to power saving techniques. One aspect of current microprocessor design practice which adversely affects power efficiency is the use of a high-speed clock to control the operation of the pipeline. This clock forces the inclusion of large sections of logic which are normally redundant but which are required to ensure that rare worst cases complete within the clock cycle time. The clock also causes power to be dissipated in all the systems on a chip, whether or not they are performing a useful function at the time. Modern power-sensitive design attempts to reduce this wastage by gating the clocks to independent function units so that they can be turned off when not needed.
ASYNCHRONOUS DESIGN
Asynchronous design, whilst offering the potential advantages for power-saving outlined above, also introduces a number of new difficulties: where independent function units wish to cornmunicate information, synchronization must be explicit; when independent units share a common resource in a non-deterministic fashion, arbiters capable of handling metastability reliably must be system must be free from dead lock (and live lock).The approach taken on AMULET1 is based on Sutherland's micropipeline. Here all activity is data driven: a new data value arrives at a function unit in normal binary encoding on a bus; its presence then signalled to the unit by a transition on the Request wire. This transition causes the unit to accept that data, signalling the acceptance by making a transition on the Acknowledge Wire. The data can then change to its next value. The request-acknowledge signalling supports full flow control at every communication interface in the design. Sutherland proposed a special form of 'capture-pass' latch for use in micro pipelines which requires 24 transistors per bit. A revised form of this latch is illustrated in figure (3) where the transistor count has been reduced to 18 per bit.