05-09-2012, 04:41 PM
A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools
[attachment=33465]
Abstract
Many ISA-level machine description languages have
been introduced to support the automated development and
retargeting of digital signal processor (DSP) software
development tools. These languages have yet to move
below the ISA-level and adequately address DSP pipeline
issues. ISA-level bit-accurate models may be reasonable
for small micro-controllers, but are inadequate when
applied to complex high-performance DSPs. We introduce
a new machine description language, RADL, which supports
the automated generation of DSP programming
tools. From RADL, we can generate production-quality
tools including cycle- and phase-accurate simulators.
RADL has explicit support for pipeline modeling, including
delay slots, interrupts, hardware loops, hazards, and multiple
interacting pipelines in a natural and intuitive way.
RADL can represent both SIMD and MIMD instruction
styles. We have coupled our language to an in-house toolchain
generator which is used to create production assemblers,
simulators and compilers.
Introduction
Time-to-market pressures in telecommunications and
consumer electronics are in direct conflict with the increasing
complexity of today's embedded hardware designs.
These designs are increasingly turning to programmable
DSP core processors employed in conjunction with custom
circuitry. DSP core designs are themselves evolving. To
meet these pressures it is necessary to be able to reuse
application and hardware designs as well as to be able to
generate programming tools for those hardware designs.
Early availability of assemblers, instruction-set simulators,
and compilers are required to meet market pressures
in developing new cost-effective applications. Manual
development of such production-quality tools is simply too
slow; hence, the need for retargetable programming tools.
As pointed out by Fauth et al [1], such tools can even be
used as aids to architecture exploration, if they can be generated
fast enough. However, we do not wish to sacrifice
tool quality. ISA-level retargeting leading to bit-accurate
tools may be reasonable for micro-controllers, but is inadequate
when applied to complex high-performance embedded
DSP designs.
Previous work
We have designed a new machine description language
because no existing system includes an ISA-level description
with a simple to use yet detailed pipeline model suitable
for embedded DSPs.
The nML processor description language [1-5] is the
closest to our work. It includes the concepts of an operation
hierarchy, separate specification of assembly language
syntax, machine language encoding and simulator/compiler
behavior. All these appear in RADL (Retargetable
Architecture Description Language), albeit, in a somewhat
different syntactic form. However, nML handles a pipeline
only awkwardly [5]. It also includes an implicit program
counter, which is inconvenient in some circumstances such
as hardware or zero-overhead loops and interrupts, and the
handling of delay slots is very limited. Resources (e.g.,
registers, etc.) are global, only, which complicates descriptions.
Operation Hierarchy
In order to understand how to introduce multiple pipelines
we need to make a brief excursion into hierarchical
operations. A processor is described as a nested hierarchy
of operations and sub-operations, as is done in nML [2].
The root of the hierarchy is marked as a "main" operation.
The hierarchical relationships of operations are specified in
the composition sections of those operations. This corresponds
to nML's And- and Or-rules, except that in RADL
we can combine both rules into a single composition statement.
Conclusions
This paper has introduced a flexible and effective
approach to the task of modeling processors with multiple
pipelines for the purpose of retargetable production-quality
programming tools. The focus has been primarily on
cycle- and phase-accurate simulators. The main contributions
are in the ease and flexibility of capturing pipeline
behavior and in inter-pipeline control and data communications.
Examples were presented of a machine description
of the familiar and accessible DLX pedagogical processor
described in Hennessy and Patterson [12].
RADL demonstrates that the description of pipelines in
support of tool retargetability can be achieved in a straightforward
and intuitive manner. Typical pipeline aspects
such as control signals, stall strategies and latch registers
are made explicit in RADL. Many of the tedious issues
such as copying unchanged latch fields to the next latch
register and resetting control signals are handled automatically.
The pipeline representation is sufficiently close to
typical processor descriptions (e.g., H&P figures in Chapter
3) that it is very easy to write a RADL description from
such hardware descriptions. This improves both visibility
into a processor description and the ease with which it can
be modified.
[attachment=33465]
Abstract
Many ISA-level machine description languages have
been introduced to support the automated development and
retargeting of digital signal processor (DSP) software
development tools. These languages have yet to move
below the ISA-level and adequately address DSP pipeline
issues. ISA-level bit-accurate models may be reasonable
for small micro-controllers, but are inadequate when
applied to complex high-performance DSPs. We introduce
a new machine description language, RADL, which supports
the automated generation of DSP programming
tools. From RADL, we can generate production-quality
tools including cycle- and phase-accurate simulators.
RADL has explicit support for pipeline modeling, including
delay slots, interrupts, hardware loops, hazards, and multiple
interacting pipelines in a natural and intuitive way.
RADL can represent both SIMD and MIMD instruction
styles. We have coupled our language to an in-house toolchain
generator which is used to create production assemblers,
simulators and compilers.
Introduction
Time-to-market pressures in telecommunications and
consumer electronics are in direct conflict with the increasing
complexity of today's embedded hardware designs.
These designs are increasingly turning to programmable
DSP core processors employed in conjunction with custom
circuitry. DSP core designs are themselves evolving. To
meet these pressures it is necessary to be able to reuse
application and hardware designs as well as to be able to
generate programming tools for those hardware designs.
Early availability of assemblers, instruction-set simulators,
and compilers are required to meet market pressures
in developing new cost-effective applications. Manual
development of such production-quality tools is simply too
slow; hence, the need for retargetable programming tools.
As pointed out by Fauth et al [1], such tools can even be
used as aids to architecture exploration, if they can be generated
fast enough. However, we do not wish to sacrifice
tool quality. ISA-level retargeting leading to bit-accurate
tools may be reasonable for micro-controllers, but is inadequate
when applied to complex high-performance embedded
DSP designs.
Previous work
We have designed a new machine description language
because no existing system includes an ISA-level description
with a simple to use yet detailed pipeline model suitable
for embedded DSPs.
The nML processor description language [1-5] is the
closest to our work. It includes the concepts of an operation
hierarchy, separate specification of assembly language
syntax, machine language encoding and simulator/compiler
behavior. All these appear in RADL (Retargetable
Architecture Description Language), albeit, in a somewhat
different syntactic form. However, nML handles a pipeline
only awkwardly [5]. It also includes an implicit program
counter, which is inconvenient in some circumstances such
as hardware or zero-overhead loops and interrupts, and the
handling of delay slots is very limited. Resources (e.g.,
registers, etc.) are global, only, which complicates descriptions.
Operation Hierarchy
In order to understand how to introduce multiple pipelines
we need to make a brief excursion into hierarchical
operations. A processor is described as a nested hierarchy
of operations and sub-operations, as is done in nML [2].
The root of the hierarchy is marked as a "main" operation.
The hierarchical relationships of operations are specified in
the composition sections of those operations. This corresponds
to nML's And- and Or-rules, except that in RADL
we can combine both rules into a single composition statement.
Conclusions
This paper has introduced a flexible and effective
approach to the task of modeling processors with multiple
pipelines for the purpose of retargetable production-quality
programming tools. The focus has been primarily on
cycle- and phase-accurate simulators. The main contributions
are in the ease and flexibility of capturing pipeline
behavior and in inter-pipeline control and data communications.
Examples were presented of a machine description
of the familiar and accessible DLX pedagogical processor
described in Hennessy and Patterson [12].
RADL demonstrates that the description of pipelines in
support of tool retargetability can be achieved in a straightforward
and intuitive manner. Typical pipeline aspects
such as control signals, stall strategies and latch registers
are made explicit in RADL. Many of the tedious issues
such as copying unchanged latch fields to the next latch
register and resetting control signals are handled automatically.
The pipeline representation is sufficiently close to
typical processor descriptions (e.g., H&P figures in Chapter
3) that it is very easy to write a RADL description from
such hardware descriptions. This improves both visibility
into a processor description and the ease with which it can
be modified.