22-09-2012, 02:27 PM
A BUS ENCODING TO REDUCE CROSSTALK NOISE EFFECT IN SYSTEM ON CHIP
[attachment=34368]
ABSTRACT
This paper proposes a new bus coding scheme for reducing the crosstalk in System on chip(soc). As
circuit geometries become smaller, wire interconnections become closer together and taller, thus
increasing the cross-coupling capacitance between nets. At the same time, parasitic capacitance to the
substrate becomes less as interconnections become narrower, and cell delays are reduced as transistors
become smaller. With circuit geometries at 0.25 micron and above, substrate capacitance is usually the
dominant effect. However, with geometries at 0.18 micron and below, the coupling capacitance between
nets becomes significant, making crosstalk analysis increasingly important for accurate timing analysis.
We show experimentally that the proposed codes allow reducing crosstalk delay by at least 14% based on
available data.
INTRODUCTION
As device geometries shrink, chip sizes increase, and clock speeds get faster, interconnect delay
is becoming increasingly significant. Signal integrity is the ability of an electrical signal to carry
information reliably and resist the effects of high-frequency electromagnetic interference from
nearby signals. Crosstalk is the undesirable electrical interaction between two or more
physically adjacent nets due to capacitive cross-coupling. As integrated circuit technologies
advance toward smaller geometries, crosstalk effects become increasingly important compared
to cell delays and net delays.
In particular, the propagation delay through long cross-chip buses is already proving to be a
limiting factor in the speed of some designs, and this trend will only get worse. It has been
shown that the delay through a long bus is strongly a function of the coupling capacitance
between the wires. Especially detrimental to the delay is the Miller-like effect when adjacent
wires simultaneously transition in opposite directions. When the cross-coupling capacitance is
comparable to or exceeds the loading capacitance on the wires, the delay of such a transition
may be twice or more that of a wire transitioning next to a steady signal. We call this delay
penalty the “crosstalk delay”. In some high-speed designs where crosstalk delay would have
limited the clock speed, the technique of shielding was used. This involves putting a grounded
wire between every signal wire on the bus. Although this certainly is effective in preventing
crosstalk within the bus, it has the effect of doubling the wiring area.
PRELIMINARIES OF CROSSTALK EFFECTS
Crosstalk can affect signal delays by changing the times at which signal transitions occur. For
example, consider the signal waveforms on the cross-coupled nets A, B, and C in fig. 1.
Because of capacitive cross-coupling, the transitions on net A and net C can affect the time at
which the transition occurs on net B. A rising-edge transition on net A at the time shown in Fig.
1 can cause the transition to occur later on net B, possibly contributing to a setup violation for a
path containing B. Similarly, a falling-edge transition on net C can cause the transition to occur
earlier on net B, possibly contributing to a hold violation for a path containing B.
COMPARISON TO OTHER TECHNIQUES
This paper is based on the Theoretical concepts proposed in [7]. The encoder presented in fig 4
that takes the code words of our codes has a data arrival time of 1.5ns compared to encoder
proposed in [7] has a data arrival time of 1.75ns. When the data arrival time is small, that
creates a more positive slack. In the literature, there are a number of other techniques designed
for combating crosstalk. Many of them, such as those described in [1], [2] and [3], employ
creative routing strategies in order to minimize crosstalk delay within a data path or logic block.
Our technique on the other hand, is intended for use with long, straight buses, and thus these
routing schemes are not applicable to our domain of interest. [8] and [9] mention some
techniques that are more relevant, such as skewing the timing of signals on adjacent wires,
interleaving mutually exclusive buses, and precharging the bus. However, skewing requires
careful, technology-dependent circuit design and brings up tricky timing issues, whereas our
technique is technology-independent and fully synchronous, with the crosstalk immunity
“correct by construction.” Interleaving is a useful technique, but it cannot be used with buses
that are allowed to transition on any and every clock cycle. Precharging a long bus can incur
detrimental power costs, and is usually not an option. Probably the most common technique is
simply using large repeaters to drive the Miller capacitance through brute force [10]. A
quantitative comparison between our technique and optimally-sized repeaters is technology- and
implementation-dependent. However, conceptually, using large repeaters is a power-hungry
technique, and shielding is an area-hungry technique. Crosstalk-immune bus encoding avoids
crosstalk delay with a modest impact on either area or power.
CONCLUSIONS
Cross-talk between wires of an on-chip bus is becoming a significant problem in deep submicron
IC design. Crosstalk can result in significant delay variations as well as signal integrity
problems. In this paper, we have introduced the concept of using data encoding to mitigate
crosstalk delay on buses, and we presented a practical framework for understanding crosstalk
immune coding. Current research is to design an efficient encoder and decoder to reduce
crosstalk in on chip buses. The encoder and decoder proposed in our paper reduce crosstalk
delay about 14% to that of available techniques.
[attachment=34368]
ABSTRACT
This paper proposes a new bus coding scheme for reducing the crosstalk in System on chip(soc). As
circuit geometries become smaller, wire interconnections become closer together and taller, thus
increasing the cross-coupling capacitance between nets. At the same time, parasitic capacitance to the
substrate becomes less as interconnections become narrower, and cell delays are reduced as transistors
become smaller. With circuit geometries at 0.25 micron and above, substrate capacitance is usually the
dominant effect. However, with geometries at 0.18 micron and below, the coupling capacitance between
nets becomes significant, making crosstalk analysis increasingly important for accurate timing analysis.
We show experimentally that the proposed codes allow reducing crosstalk delay by at least 14% based on
available data.
INTRODUCTION
As device geometries shrink, chip sizes increase, and clock speeds get faster, interconnect delay
is becoming increasingly significant. Signal integrity is the ability of an electrical signal to carry
information reliably and resist the effects of high-frequency electromagnetic interference from
nearby signals. Crosstalk is the undesirable electrical interaction between two or more
physically adjacent nets due to capacitive cross-coupling. As integrated circuit technologies
advance toward smaller geometries, crosstalk effects become increasingly important compared
to cell delays and net delays.
In particular, the propagation delay through long cross-chip buses is already proving to be a
limiting factor in the speed of some designs, and this trend will only get worse. It has been
shown that the delay through a long bus is strongly a function of the coupling capacitance
between the wires. Especially detrimental to the delay is the Miller-like effect when adjacent
wires simultaneously transition in opposite directions. When the cross-coupling capacitance is
comparable to or exceeds the loading capacitance on the wires, the delay of such a transition
may be twice or more that of a wire transitioning next to a steady signal. We call this delay
penalty the “crosstalk delay”. In some high-speed designs where crosstalk delay would have
limited the clock speed, the technique of shielding was used. This involves putting a grounded
wire between every signal wire on the bus. Although this certainly is effective in preventing
crosstalk within the bus, it has the effect of doubling the wiring area.
PRELIMINARIES OF CROSSTALK EFFECTS
Crosstalk can affect signal delays by changing the times at which signal transitions occur. For
example, consider the signal waveforms on the cross-coupled nets A, B, and C in fig. 1.
Because of capacitive cross-coupling, the transitions on net A and net C can affect the time at
which the transition occurs on net B. A rising-edge transition on net A at the time shown in Fig.
1 can cause the transition to occur later on net B, possibly contributing to a setup violation for a
path containing B. Similarly, a falling-edge transition on net C can cause the transition to occur
earlier on net B, possibly contributing to a hold violation for a path containing B.
COMPARISON TO OTHER TECHNIQUES
This paper is based on the Theoretical concepts proposed in [7]. The encoder presented in fig 4
that takes the code words of our codes has a data arrival time of 1.5ns compared to encoder
proposed in [7] has a data arrival time of 1.75ns. When the data arrival time is small, that
creates a more positive slack. In the literature, there are a number of other techniques designed
for combating crosstalk. Many of them, such as those described in [1], [2] and [3], employ
creative routing strategies in order to minimize crosstalk delay within a data path or logic block.
Our technique on the other hand, is intended for use with long, straight buses, and thus these
routing schemes are not applicable to our domain of interest. [8] and [9] mention some
techniques that are more relevant, such as skewing the timing of signals on adjacent wires,
interleaving mutually exclusive buses, and precharging the bus. However, skewing requires
careful, technology-dependent circuit design and brings up tricky timing issues, whereas our
technique is technology-independent and fully synchronous, with the crosstalk immunity
“correct by construction.” Interleaving is a useful technique, but it cannot be used with buses
that are allowed to transition on any and every clock cycle. Precharging a long bus can incur
detrimental power costs, and is usually not an option. Probably the most common technique is
simply using large repeaters to drive the Miller capacitance through brute force [10]. A
quantitative comparison between our technique and optimally-sized repeaters is technology- and
implementation-dependent. However, conceptually, using large repeaters is a power-hungry
technique, and shielding is an area-hungry technique. Crosstalk-immune bus encoding avoids
crosstalk delay with a modest impact on either area or power.
CONCLUSIONS
Cross-talk between wires of an on-chip bus is becoming a significant problem in deep submicron
IC design. Crosstalk can result in significant delay variations as well as signal integrity
problems. In this paper, we have introduced the concept of using data encoding to mitigate
crosstalk delay on buses, and we presented a practical framework for understanding crosstalk
immune coding. Current research is to design an efficient encoder and decoder to reduce
crosstalk in on chip buses. The encoder and decoder proposed in our paper reduce crosstalk
delay about 14% to that of available techniques.