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Full Version: The ARM9 Family - High Performance Microprocessors for Embedded Applications
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The ARM9 Family - High Performance Microprocessors for Embedded Applications

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What is ARM

Reduced Instruction Set Computer RISC.
Designs and ARM Architecture licensed by ARM Ltd.
Produced by: Intel, Philips, TI, Sharp, etc.
Popular cores: ARM7 ,ARM9.
Windows CE / PocketPC, Symbian / EPOC, Nucleus,PalmOS.

ARM 7

ARM designs high performance, low power microprocessors targeted
at embedded applications..
This product incorporates the Thumb instruction set, code density
and typically achieves around 60MHz and only 1.5 mW/MHz power
consumption on a 0.35m process.
The ARM7 family owes its success to the combination of low power,
low cost and high performance.

ARM9TDMI embedded core

The rst member of the ARM9 family is the ARM9TDMI integer core.
Higher performance has been achieved by increasing the depth of the
pipeline from 3 stages as in the ARM7TDMI to 5 stages.
This allows the device to be clocked at a higher rate than the
ARM7TDMI.
Forwarding paths have also been introduced to the pipeline in order
to reduce the number of interlock cases and hence reduce the average
number of clocks per instruction, CPI.
Load and store operations account for around 25 percentage of all
instructions in the ARM instruction
ow.

ARM9 DMI Data Path

The ARM9TDMI microarchitecture described above results in an
average CPI of 1.5.
The new microarchitecture results in a 21 percentage increase in
instruction throughput relative to ARM7TDMI and 1.1 MIPS/MHz,
compared to 0.9 MIPS/MHz.
ARM9TDMI is clocked at twice the rate of ARM7TDMI.
increase in performance requires around 50 percentage more
transistors and the area has increased by almost 90 percentage.

The ARM940T

The ARM9TDMI processor core has been integrated with caches, a
write bu er and a protection unit in the ARM940T processor.
it allows the processor to operate at its maximum frequency since
memory accesses are to the local, high performance cache.
main memory is accessed infrequently, system power is reduced.
increase in performance requires around 50 percentage more
transistors and the area has increased by almost 90 percentage.

ARM940T Architecture

The caches in the ARM940T are both 4KB in size in the rst
implementation.
The cache blocks are built using a CAM-RAM structure comprising
64 lines each with 4 words of data.
Each cache block has 64 way associativity and the CAMs are designed
to compare a maximum of 27 address bits.
Firstly, the 32 bit address from the processor is decoded to determine
which of the 4 segments the addressed data might be in. In the 4KB
ARM940T design, bits 5:4 of the address are used for the segment
decode.
Secondly, the upper 26 bits of the address are then passed into the
CAM where they are compared with the CAM contents.
Finally, if there is a CAM match, then a data access in the cache
RAM occurs. Each RAM line is 4 words long and bits 3:2 of the
address are used to select the desired word.

Conclusion

The ARM9TDMI and ARM940T have met their design goals of
providing high performance Thumb compatible processors with small
die size and low power consumption.
These products and their derivatives will serve the need of next
generation applications while ARM7TDMI continues to serve the
needs of the low end.