28-09-2012, 01:34 PM
8086 Microprocessor
[attachment=34709]
8086 Architecture
The 8086 has
20 address lines
16 data lines
4-10 control lines.
With this the 8086 is able
To address 1,048,,576 (220 ) memory locations/ports.
To manipulate and/or operate on 16-bits(2-bytes) of data at a time.
To generate necessary control signals
The internal architecture of 8086 can be mainly divided into two units:
Bus interface unit (biu)
Execution unit (eu)
The biu contains :
Code segment register (cs)
data segment register (ds)
extra segment register (es)
Stack segment registeer (ss) and
instruction pointer (ip)
The Bus Interface Unit (BIU) consists of the following:
Instruction Queue: this allows the next instructions or data to be fetched from memory while the processor is executing the current instruction.
The memory interface is usually much slower than the processor execution time, so this decouples the memory cycle time from the execution time.
Segment Registers: The Code Segment (CS), Data Segment (DS), Stack Segment (SS) and Extra Segment (ES) registers are 16-bit registers, used with the 16-bit Base registers to generate the 20-bit address required to allow the 8086/8088 to address 1Mb of memory.
They are changed under program control to point to different segments as a program executes.
The Segmented architecture was used in the 8086 to keep compatibility with earlier processors such as the 8085.
It is one of the most significant elements of the Intel Architecture
This is how memory is accessed using these signals
ALE (Address Latch Enable): On both the 8086 and 8088 processors the address and data buses are multiplexed. This means that the same pins are used to carry both address and data information – at different times during the read or write cycle. At the start of the cycle the address/data bus carries the address signals, while at the end of the cycle the pins are used for the data bus.
The ALE signal is used to allow external logic to LATCH the addresses while the AD lines carry address data and hold those addresses so that they can be applied to the other devices in the system. The address latch used are 74HC373 or equivalent parts. Unlike a flip flop, the 74HC373 is a transparent latch.
[attachment=34709]
8086 Architecture
The 8086 has
20 address lines
16 data lines
4-10 control lines.
With this the 8086 is able
To address 1,048,,576 (220 ) memory locations/ports.
To manipulate and/or operate on 16-bits(2-bytes) of data at a time.
To generate necessary control signals
The internal architecture of 8086 can be mainly divided into two units:
Bus interface unit (biu)
Execution unit (eu)
The biu contains :
Code segment register (cs)
data segment register (ds)
extra segment register (es)
Stack segment registeer (ss) and
instruction pointer (ip)
The Bus Interface Unit (BIU) consists of the following:
Instruction Queue: this allows the next instructions or data to be fetched from memory while the processor is executing the current instruction.
The memory interface is usually much slower than the processor execution time, so this decouples the memory cycle time from the execution time.
Segment Registers: The Code Segment (CS), Data Segment (DS), Stack Segment (SS) and Extra Segment (ES) registers are 16-bit registers, used with the 16-bit Base registers to generate the 20-bit address required to allow the 8086/8088 to address 1Mb of memory.
They are changed under program control to point to different segments as a program executes.
The Segmented architecture was used in the 8086 to keep compatibility with earlier processors such as the 8085.
It is one of the most significant elements of the Intel Architecture
This is how memory is accessed using these signals
ALE (Address Latch Enable): On both the 8086 and 8088 processors the address and data buses are multiplexed. This means that the same pins are used to carry both address and data information – at different times during the read or write cycle. At the start of the cycle the address/data bus carries the address signals, while at the end of the cycle the pins are used for the data bus.
The ALE signal is used to allow external logic to LATCH the addresses while the AD lines carry address data and hold those addresses so that they can be applied to the other devices in the system. The address latch used are 74HC373 or equivalent parts. Unlike a flip flop, the 74HC373 is a transparent latch.