28-09-2012, 01:38 PM
The Microprocessor and its Architecture
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Introduction
This chapter presents the microprocessor as a programmable device by first looking at its internal programming model and then how its memory space is addressed.
The architecture of Intel microprocessors is presented, as are the ways that the family members address the memory system.
Addressing modes for this powerful family of microprocessors are described for the real, protected, and flat modes of operation.
Chapter Objectives
Describe function and purpose of each program-visible register in the 8086-Core2 microprocessors, including 64-bit extensions.
Detail the flag register and the purpose of each flag bit.
Describe how memory is accessed using real mode memory-addressing techniques.
Describe how memory is accessed using protected mode memory-addressing techniques.
Describe how memory is accessed using the 64-bit flat memory model.
Describe program-invisible registers found in the 80286 through Core2 microprocessors.
Detail the operation of the memory-paging mechanism.
2–1 INTERNAL MICROPROCESSOR ARCHITECTURE
Before a program is written or instruction investigated, internal configuration of the microprocessor must be known.
In a multiple core microprocessor each core contains the same programming model.
Each core runs a separate task or thread simultaneously.
The Programming Model
8086 through Core2 considered program visible.
registers are used during programming and are specified by the instructions
Other registers considered to be program invisible.
not addressable directly during applications programming
80286 and above contain program-invisible registers to control and operate protected memory.
and other features of the microprocessor
80386 through Core2 microprocessors contain full 32-bit internal architectures.
8086 through the 80286 are fully upward-compatible to the 80386 through Core2.
Figure 2–1 illustrates the programming model 8086 through Core2 microprocessor.
including the 64-bit extensions
Multipurpose Registers
RAX - a 64-bit register (RAX), a 32-bit register (accumulator) (EAX), a 16-bit register (AX), or as either of two 8-bit registers (AH and AL).
The accumulator is used for instructions such as multiplication, division, and some of the adjustment instructions.
Intel plans to expand the address bus to 52 bits to address 4P (peta) bytes of memory.
RBX, addressable as RBX, EBX, BX, BH, BL.
BX register (base index) sometimes holds offset address of a location in the memory system in all versions of the microprocessor
RCX, as RCX, ECX, CX, CH, or CL.
a (count) general-purpose register that also holds the count for various instructions
RDX, as RDX, EDX, DX, DH, or DL.
a (data) general-purpose register
holds a part of the result from a multiplication or part of dividend before a division