29-09-2012, 12:52 PM
Designing CMOS/Molecular Memories While Considering Device Parameter Variations
[attachment=34806]
Introduction
In recent years, many advances have been made in the development of molecular scale devices.
Experimental data shows that these devices have potential use in both memory and logic.
This report describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures issues in reading and writing such as memory using CMOS circuitry.
Simulation results, incorporating experimental device data, are presented using Synopsis Hspice.
Why nanoelectronics?
To surmount the physical and economic barriers of current semiconductor technologies and continue along the exponential projections of Moore’s Law.
Unprecedented levels of device density
Low power computing,
Tight integration with other biological and chemical functions such as sensors.
Issues Around MOSFET Scaling
Dominance of non ideal I-V characteristics of Mos devices.
Scaling down the transistors is the decreased ability to handle fabrication process variations as transistors and wires become smaller, fewer atoms make up the individual parts.
The largest hurdle to further scaling of the MOSFET is simple economics
Modelling the Molecular Device
A number of non-classical characteristics.
The UDM models the I-V characteristics of such devices from
1. Linear (resistor-like) ,
2.Thermionic emission (diode equation),
3.Resonant tunnelling (Gaussian equation) and
4.Coulomb blockade (step function).
Using verilog-A model for all the above behaviours and using this .va model we modeled the molecular memory in Hspice.
Crossbar Array
The crossbar array is a plane of parallel nanowires crossing another plane of parallel nanowires perpendicularly with a SAM of molecules sandwiched in between each wire crossing.
Programmability, low-cost fabrication, and high device densities, the regularity of the crossbar structure necessitates only one mask for fabrication (for the parallel wires in plane).
Detailed Memory Operation
During a read, the first step is to force the load device to the high-conductivity state by driving Vw on the load row and −Vw on the selected column. Immediately following this, Vw is applied to the selected row in order to read the bit.
This could, and usually does, lead to a situation where the selected column is holding −Vw just as the row rises to −Vw, leading to 2Vw accross the device which rewrites it.
Thus, it is necessary to pull the selected column to ground after writing the load device and before reading the bit. In the case of the design proposed in this work, this is accomplished by using a second clock (CLK2)in addition to CLK.
Bidirectional pass-gates are used to both drive signals across the memory lines during a write and to sense the output during a read.
Methods for Reading and Writing
In addition to the row and column decoders, the CMOS layer must also include control circuitry for :
1. Driving both selected and unselected (grounded) rows during a read, 2.Applying a large positive or large negative voltage during a write, 3.Selecting between read and write operations.
These functions are most easily implemented using pass-gate or pass-transistor multiplexors, but care must be taken to ensure that the CMOS circuitry doesn’t become so dense as to negate the area advantages obtained by using nanoelectronics
[attachment=34806]
Introduction
In recent years, many advances have been made in the development of molecular scale devices.
Experimental data shows that these devices have potential use in both memory and logic.
This report describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures issues in reading and writing such as memory using CMOS circuitry.
Simulation results, incorporating experimental device data, are presented using Synopsis Hspice.
Why nanoelectronics?
To surmount the physical and economic barriers of current semiconductor technologies and continue along the exponential projections of Moore’s Law.
Unprecedented levels of device density
Low power computing,
Tight integration with other biological and chemical functions such as sensors.
Issues Around MOSFET Scaling
Dominance of non ideal I-V characteristics of Mos devices.
Scaling down the transistors is the decreased ability to handle fabrication process variations as transistors and wires become smaller, fewer atoms make up the individual parts.
The largest hurdle to further scaling of the MOSFET is simple economics
Modelling the Molecular Device
A number of non-classical characteristics.
The UDM models the I-V characteristics of such devices from
1. Linear (resistor-like) ,
2.Thermionic emission (diode equation),
3.Resonant tunnelling (Gaussian equation) and
4.Coulomb blockade (step function).
Using verilog-A model for all the above behaviours and using this .va model we modeled the molecular memory in Hspice.
Crossbar Array
The crossbar array is a plane of parallel nanowires crossing another plane of parallel nanowires perpendicularly with a SAM of molecules sandwiched in between each wire crossing.
Programmability, low-cost fabrication, and high device densities, the regularity of the crossbar structure necessitates only one mask for fabrication (for the parallel wires in plane).
Detailed Memory Operation
During a read, the first step is to force the load device to the high-conductivity state by driving Vw on the load row and −Vw on the selected column. Immediately following this, Vw is applied to the selected row in order to read the bit.
This could, and usually does, lead to a situation where the selected column is holding −Vw just as the row rises to −Vw, leading to 2Vw accross the device which rewrites it.
Thus, it is necessary to pull the selected column to ground after writing the load device and before reading the bit. In the case of the design proposed in this work, this is accomplished by using a second clock (CLK2)in addition to CLK.
Bidirectional pass-gates are used to both drive signals across the memory lines during a write and to sense the output during a read.
Methods for Reading and Writing
In addition to the row and column decoders, the CMOS layer must also include control circuitry for :
1. Driving both selected and unselected (grounded) rows during a read, 2.Applying a large positive or large negative voltage during a write, 3.Selecting between read and write operations.
These functions are most easily implemented using pass-gate or pass-transistor multiplexors, but care must be taken to ensure that the CMOS circuitry doesn’t become so dense as to negate the area advantages obtained by using nanoelectronics