29-09-2012, 04:56 PM
Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery
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Abstract
In a clock distribution network, process variations, and environmental variations introduce skew and jitter. With increasing demand for higher performance and faster chips, increasing the operating clock frequency is an inevitable consequence. A faster clock frequency corresponds to a tighter clock period and requires strict limits on clock uncertainties. Optical clock distribution has immense potential to improve clock skew, jitter. A practical on-chip optical clocking system must be CMOS compatible in order to provide attractive cost effectiveness for system level integration and ease of manufacturing. Key advantages of optical clock distribution over electrical clock distribution are reduction in clock skew, delay. Optical clock distribution technique is considered to be a good alternative to conventional methods of balancing clock trees and clock buffers to reduce skew and jitter.
[attachment=34850]
Abstract
In a clock distribution network, process variations, and environmental variations introduce skew and jitter. With increasing demand for higher performance and faster chips, increasing the operating clock frequency is an inevitable consequence. A faster clock frequency corresponds to a tighter clock period and requires strict limits on clock uncertainties. Optical clock distribution has immense potential to improve clock skew, jitter. A practical on-chip optical clocking system must be CMOS compatible in order to provide attractive cost effectiveness for system level integration and ease of manufacturing. Key advantages of optical clock distribution over electrical clock distribution are reduction in clock skew, delay. Optical clock distribution technique is considered to be a good alternative to conventional methods of balancing clock trees and clock buffers to reduce skew and jitter.