02-10-2012, 05:44 PM
Introduction to FPGA System Design
[attachment=35089]
Introduction
Field programmable gate arrays (FPGAs) are powerful devices for implementing complex digital systems. FPGAs are best used with an understanding of the key differences between FPGAs
and previous logic technologies (like PLDs or SSI/MSI). Understanding these differences and using design techniques appropriate for FPGAs result in 50%-100% improvement in speed and
density compared to design styles that treat FPGAs and PLDs or SSI/MSI equally. This application note identifies the key architectural differences between FPGAs, PLDs, and SSI/MSI,
explains design methodologies that result from understanding these differences, and gives some simple examples illustrating these techniques in real applications.
FPGAs Compared to PLDs
PLDs are array-oriented devices that typically have an AND--OR structure with wide input AND gates feeding a narrower OR gate. A register is typically available at the output of each OR.
This architecture is termed "logic rich" because there are typically many more logic gates than register gates - the ratio can be as much as 5 to 1. PLDs pay a significant speed penalty when
multiple levels of logic are required because of the large delay through the wider logic modules. Speeds tend to be more predictable in PLDs because of the larger "speed quanta".
FPGAs, on the other hand, are register rich, with a logic to register ratio closer to 2 to 1. This ratio is equivalent to traditional gate array usage ratios and tends to be related to the fact that high
density designs (more than 1K gates) need more registers than the traditional "glue" oriented low density (less them 1K gates) applications. FPGA logic structures are optimized for functions
narrower than PLDs. FPGAs have a smaller speed quanta than PLDs, so logic functions can be incremented in complexity while incrementing the delay only a little each time. Additionally,
signals that need to be fast can be sourced near the bottom of the logic tree, minimizing the number of logic levels required, while slow signals can be sourced at the top of the logic tree, where
more logic levels are required.
FPGAs Compared to SSI/MSI
SSI/MSI building blocks are created by optimizing the number of pins on popular functions to fit in the small packages available. Logic functions are typically constructed of a few hundred
popular building blocks like counters, multiplexers, shift registers, and comparators. The typical design is optimized to reduce package count, and "tricks" have evolved to make the most use of
a device. For example, simple state machines are constructed from counters and decoders with appropriate pins tied to one or zero. This technique minimizes package count compared to a
package-intensive gate-for-gate design. The interconnections in these designs are done on the PC board, causing insignificant timing delays.
FPGA Design Techniques
Understanding the main differences between FPGAs, PLDs, and SSI/MSI devices is the first step towards creating efficient FPGA designs. The next step is to understand efficient FPGA design
techniques. Techniques will be described by grouping them as state machine, data path, and random logic functions.
State Machine Oriented Techniques
The traditional PLD design techniques for implementing state machines are geared toward the logic rich and register lean architecture of the standard PLD. A small number of state registers are
used (usually the theoretical minimum), since registers are scarce. This requires a larger amount of combinatorial logic to decode the state, but PLDs usually are able to provide enough
combinatorial logic to do this effectively. Using this technique for FPGAs would not be an efficient use of FPGA strengths-numerous registers and fast narrow logic gates. A bit-per-state
approach to state machine design, where each state uses a separate register instead of encoding states in multiple registers, results in faster and more efficient state machines in FPGAs. In
many cases, speed improves by 50 percent to 100 percent compared to the PLD-oriented methodology of an encoded state machine.
In PLD-oriented designs, logic is typically used to develop outputs from state machines. Usually this requires an additional level of logic after the state register and adds delay. In FPGAs, this
level of logic can be eliminated in many cases by combining the logic in front of the state bits in which an output is active. For example, if the CE output from a state machine needs to be active
in states 3 and 5, the logic feeding state bits 3 and 5 can be ORed together and registered to create the CE output without incurring a logic delay after the register. Since the logic in front of
state bits is simple, usually no additions delay or logic resources are required in front of the new register.
Another popular state machine design technique for PLDs uses counters to generate a sequence of wait states. For example, a state machine may need to wait for 16 cycles until a data transfer
can begin. A four-bit counter can be used to generate the required state sequence. This is fairly efficient in PLD architectures because of the logic rich and register lean characteristics of the
count function. It is not as good a fit for FPGAs, however. In FPGAs, registers are rich and a shift register is more efficient and faster than a counter. A normal shift register will require one
register per wait state. If very large delays are required, a feedback shift register can be used that implements only one state less than a counter, but requires much less logic and is significantly
faster.
[attachment=35089]
Introduction
Field programmable gate arrays (FPGAs) are powerful devices for implementing complex digital systems. FPGAs are best used with an understanding of the key differences between FPGAs
and previous logic technologies (like PLDs or SSI/MSI). Understanding these differences and using design techniques appropriate for FPGAs result in 50%-100% improvement in speed and
density compared to design styles that treat FPGAs and PLDs or SSI/MSI equally. This application note identifies the key architectural differences between FPGAs, PLDs, and SSI/MSI,
explains design methodologies that result from understanding these differences, and gives some simple examples illustrating these techniques in real applications.
FPGAs Compared to PLDs
PLDs are array-oriented devices that typically have an AND--OR structure with wide input AND gates feeding a narrower OR gate. A register is typically available at the output of each OR.
This architecture is termed "logic rich" because there are typically many more logic gates than register gates - the ratio can be as much as 5 to 1. PLDs pay a significant speed penalty when
multiple levels of logic are required because of the large delay through the wider logic modules. Speeds tend to be more predictable in PLDs because of the larger "speed quanta".
FPGAs, on the other hand, are register rich, with a logic to register ratio closer to 2 to 1. This ratio is equivalent to traditional gate array usage ratios and tends to be related to the fact that high
density designs (more than 1K gates) need more registers than the traditional "glue" oriented low density (less them 1K gates) applications. FPGA logic structures are optimized for functions
narrower than PLDs. FPGAs have a smaller speed quanta than PLDs, so logic functions can be incremented in complexity while incrementing the delay only a little each time. Additionally,
signals that need to be fast can be sourced near the bottom of the logic tree, minimizing the number of logic levels required, while slow signals can be sourced at the top of the logic tree, where
more logic levels are required.
FPGAs Compared to SSI/MSI
SSI/MSI building blocks are created by optimizing the number of pins on popular functions to fit in the small packages available. Logic functions are typically constructed of a few hundred
popular building blocks like counters, multiplexers, shift registers, and comparators. The typical design is optimized to reduce package count, and "tricks" have evolved to make the most use of
a device. For example, simple state machines are constructed from counters and decoders with appropriate pins tied to one or zero. This technique minimizes package count compared to a
package-intensive gate-for-gate design. The interconnections in these designs are done on the PC board, causing insignificant timing delays.
FPGA Design Techniques
Understanding the main differences between FPGAs, PLDs, and SSI/MSI devices is the first step towards creating efficient FPGA designs. The next step is to understand efficient FPGA design
techniques. Techniques will be described by grouping them as state machine, data path, and random logic functions.
State Machine Oriented Techniques
The traditional PLD design techniques for implementing state machines are geared toward the logic rich and register lean architecture of the standard PLD. A small number of state registers are
used (usually the theoretical minimum), since registers are scarce. This requires a larger amount of combinatorial logic to decode the state, but PLDs usually are able to provide enough
combinatorial logic to do this effectively. Using this technique for FPGAs would not be an efficient use of FPGA strengths-numerous registers and fast narrow logic gates. A bit-per-state
approach to state machine design, where each state uses a separate register instead of encoding states in multiple registers, results in faster and more efficient state machines in FPGAs. In
many cases, speed improves by 50 percent to 100 percent compared to the PLD-oriented methodology of an encoded state machine.
In PLD-oriented designs, logic is typically used to develop outputs from state machines. Usually this requires an additional level of logic after the state register and adds delay. In FPGAs, this
level of logic can be eliminated in many cases by combining the logic in front of the state bits in which an output is active. For example, if the CE output from a state machine needs to be active
in states 3 and 5, the logic feeding state bits 3 and 5 can be ORed together and registered to create the CE output without incurring a logic delay after the register. Since the logic in front of
state bits is simple, usually no additions delay or logic resources are required in front of the new register.
Another popular state machine design technique for PLDs uses counters to generate a sequence of wait states. For example, a state machine may need to wait for 16 cycles until a data transfer
can begin. A four-bit counter can be used to generate the required state sequence. This is fairly efficient in PLD architectures because of the logic rich and register lean characteristics of the
count function. It is not as good a fit for FPGAs, however. In FPGAs, registers are rich and a shift register is more efficient and faster than a counter. A normal shift register will require one
register per wait state. If very large delays are required, a feedback shift register can be used that implements only one state less than a counter, but requires much less logic and is significantly
faster.