06-10-2012, 04:48 PM
PROCESSOR 8087
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NUMERIC PROCESSOR 8087
A most preliminary form of a multiprocessor system is a system containing a CPU and coprocessors. The numeric processor 8087 is a coprocessor which has been designed to work under the control of the processor 8086 and offer it additional numeric processing capabilities, packaged in a 40 pin ceramic DIP package, it is available in5 MHz, 8MHz and 10MHz versions compatible with 8086, 8088, 80186 and 80188 processors.
The 8086 is supposed to perform the opcode fetch cycles and identify the instructions for 8087. Once the instruction for 8087 is identified by 8086, it is allotted to 8087 for further execution. Thus 8086-8087 couplet implements instruction level master-slave configuration. After the completion of the 8087 execution cycle, the results may be referred back to the CPU. Thus the operation of the processor 8087 is transparent to the programmer. The 8087 instructions may lie interleaved in the 8086 program as if they belong to the 8086 instruction set. It is the task of 8086 to identify the 8087 instructions from the program, send it to 8087 for execution and get back the results. The operation of 8087 does not need any software support from the system software or operating system. The 8087 adds 68 new instructions to the instruction set of 8086.
Architecture of 8087
The internal architecture of 8087 is shown in Fig. 3.1(a). The 8087 is divided into two sections internally. The control unit (CU) and the numeric extension unit (NEU). The numeric extension unit executes all the numeric processor instructions while the control unit (CU) receives, decodes instructions, reads and writes memory operands and executes the 8087 control instructions. These two units may work asynchronously with each other. The control unit is mainly responsible for establishing communication between the CPU and memory and also for coordinating the internal coprocessor execution. The CPU, while fetching the instructions from memory, monitors the data bus to check for the 8087 instructions. The 8087 CU internally maintains a parallel queue, identical to the status queue of the main CPU. The CU automatically monitors the /S7 line to detect the CPU type, i.e. 8086 or 8088 and accordingly adjusts the queue length. The 8087 further uses the QS0 and QS1 pins to obtain and identify the instructions fetched by the host CPU. The host CPU identifies the coprocessor instructions using the ESCAPE code bits in them. Once the CPU recognizes the ESCAPE code, it triggers the execution of the numeric processor instruction in 8087.
Interconnections of 8087 with the 8086
The communication between 8087 and the host CPU has already been discussed in Section 8.3.1. In this section, we study the physical interconnections of 8087 with 8086/8088 and 80186/80188. 8087 can be connected with any of these CPUs only in their maximum mode of operation, i.e. only when the MN/ pin of the CPU is grounded. In maximum mode, all the control signals are derived using a separate chip known as bus controller. The 8288 is 8086/ 88 compatible bus controller while 82188 is 80186/80188 compatible bus controller.
PROTECTED VIRTUAL ADDRESS MODE (PVAM)
The 80286 is the first processor to support the concepts of virtual memory and memory management. The virtual memory does not exist physically but still it appears to the programmer that it is available in the system. The concept of virtual memory is implemented using physical memory that the CPU can directly access rand secondary memory that is used as storage for data and program. The data and program are stored in secondary memory initially. The segment of the program or data, required for actual execution at that instant, is fetched from the secondary memory into physical memory. After the execution of this fetched segment, the next segment required for further execution is again fetched from the secondary memory, while the results of the executed segment are stored back into the secondary memory for further references. This continues till the complete program is executed. During the execution, the partial results of the previously executed portions are again fetched into the physical memory, if required for further execution. The procedure of fetching the chosen program segments or data from the secondary storage into the physical memory is called ‘swapping’.
[attachment=35568]
NUMERIC PROCESSOR 8087
A most preliminary form of a multiprocessor system is a system containing a CPU and coprocessors. The numeric processor 8087 is a coprocessor which has been designed to work under the control of the processor 8086 and offer it additional numeric processing capabilities, packaged in a 40 pin ceramic DIP package, it is available in5 MHz, 8MHz and 10MHz versions compatible with 8086, 8088, 80186 and 80188 processors.
The 8086 is supposed to perform the opcode fetch cycles and identify the instructions for 8087. Once the instruction for 8087 is identified by 8086, it is allotted to 8087 for further execution. Thus 8086-8087 couplet implements instruction level master-slave configuration. After the completion of the 8087 execution cycle, the results may be referred back to the CPU. Thus the operation of the processor 8087 is transparent to the programmer. The 8087 instructions may lie interleaved in the 8086 program as if they belong to the 8086 instruction set. It is the task of 8086 to identify the 8087 instructions from the program, send it to 8087 for execution and get back the results. The operation of 8087 does not need any software support from the system software or operating system. The 8087 adds 68 new instructions to the instruction set of 8086.
Architecture of 8087
The internal architecture of 8087 is shown in Fig. 3.1(a). The 8087 is divided into two sections internally. The control unit (CU) and the numeric extension unit (NEU). The numeric extension unit executes all the numeric processor instructions while the control unit (CU) receives, decodes instructions, reads and writes memory operands and executes the 8087 control instructions. These two units may work asynchronously with each other. The control unit is mainly responsible for establishing communication between the CPU and memory and also for coordinating the internal coprocessor execution. The CPU, while fetching the instructions from memory, monitors the data bus to check for the 8087 instructions. The 8087 CU internally maintains a parallel queue, identical to the status queue of the main CPU. The CU automatically monitors the /S7 line to detect the CPU type, i.e. 8086 or 8088 and accordingly adjusts the queue length. The 8087 further uses the QS0 and QS1 pins to obtain and identify the instructions fetched by the host CPU. The host CPU identifies the coprocessor instructions using the ESCAPE code bits in them. Once the CPU recognizes the ESCAPE code, it triggers the execution of the numeric processor instruction in 8087.
Interconnections of 8087 with the 8086
The communication between 8087 and the host CPU has already been discussed in Section 8.3.1. In this section, we study the physical interconnections of 8087 with 8086/8088 and 80186/80188. 8087 can be connected with any of these CPUs only in their maximum mode of operation, i.e. only when the MN/ pin of the CPU is grounded. In maximum mode, all the control signals are derived using a separate chip known as bus controller. The 8288 is 8086/ 88 compatible bus controller while 82188 is 80186/80188 compatible bus controller.
PROTECTED VIRTUAL ADDRESS MODE (PVAM)
The 80286 is the first processor to support the concepts of virtual memory and memory management. The virtual memory does not exist physically but still it appears to the programmer that it is available in the system. The concept of virtual memory is implemented using physical memory that the CPU can directly access rand secondary memory that is used as storage for data and program. The data and program are stored in secondary memory initially. The segment of the program or data, required for actual execution at that instant, is fetched from the secondary memory into physical memory. After the execution of this fetched segment, the next segment required for further execution is again fetched from the secondary memory, while the results of the executed segment are stored back into the secondary memory for further references. This continues till the complete program is executed. During the execution, the partial results of the previously executed portions are again fetched into the physical memory, if required for further execution. The procedure of fetching the chosen program segments or data from the secondary storage into the physical memory is called ‘swapping’.