09-10-2012, 01:00 PM
Finfet
[attachment=35749]
Introduction
As devices are shrinking further and further it will be difficult to work with conventional mosfet.
Going down to 45nm technology and further down there are n number of problem links to the conventional mosfet .
Severe short channel effect such as DIBL, sub threshold leakage, gate tunneling and some second order effect.
In order to compensate one problem it leads to another problem as channel length is decreasing with growing technology.
Now it is felt that instead of planner mosfet , a double gate device is needed at a gate length below 50 nm in order follow the Moore's law for little more time.
Short channel effect
As the channel L is reduce to increase both speed and no. of device per chip the so called short channel effect arises.
Five type of short channel effect are there:-
DIBL and pinch through
Surface scattering
velocity saturation
Impact ionization
Hot electron effect
What is Finfet?
The term FINFET coined by university of California Berkeley researcher.
To describe a non planner ,double gate transistor built on a SOI insulator substrate.
Distinguish characteristic of Finfet is that the conducting channel is wrapped by a thin silicon “FIN” which form the body of device
Thickness of fin determine the effective channel length of the device
Finfet structure
Up manufacturer like AMD,MOTOROLA,IBM describe their double gate effort as the FINFET development where as INTEL avoid using the term.
In technical literature FINFET is used some what generically to describe any fin based, multi gate transistor architecture regardless of the number of gates.
Advantage of Finfet
Having excellent control on short channel effect in submicron regime and transistor still scalable.
Much lower off state current compared to bulk counterpart.
Application
Low power design in digital circuit such as RAM, because of its low off state current.
Power amplifier or other appliction in analog area which require good linearity.
Conclusion
Finfet appear to be the device of choice in sub 50 nm design because of their reduce short channel effect.
They seem well suited to keep us on track of moore’s law for little longer time.
[attachment=35749]
Introduction
As devices are shrinking further and further it will be difficult to work with conventional mosfet.
Going down to 45nm technology and further down there are n number of problem links to the conventional mosfet .
Severe short channel effect such as DIBL, sub threshold leakage, gate tunneling and some second order effect.
In order to compensate one problem it leads to another problem as channel length is decreasing with growing technology.
Now it is felt that instead of planner mosfet , a double gate device is needed at a gate length below 50 nm in order follow the Moore's law for little more time.
Short channel effect
As the channel L is reduce to increase both speed and no. of device per chip the so called short channel effect arises.
Five type of short channel effect are there:-
DIBL and pinch through
Surface scattering
velocity saturation
Impact ionization
Hot electron effect
What is Finfet?
The term FINFET coined by university of California Berkeley researcher.
To describe a non planner ,double gate transistor built on a SOI insulator substrate.
Distinguish characteristic of Finfet is that the conducting channel is wrapped by a thin silicon “FIN” which form the body of device
Thickness of fin determine the effective channel length of the device
Finfet structure
Up manufacturer like AMD,MOTOROLA,IBM describe their double gate effort as the FINFET development where as INTEL avoid using the term.
In technical literature FINFET is used some what generically to describe any fin based, multi gate transistor architecture regardless of the number of gates.
Advantage of Finfet
Having excellent control on short channel effect in submicron regime and transistor still scalable.
Much lower off state current compared to bulk counterpart.
Application
Low power design in digital circuit such as RAM, because of its low off state current.
Power amplifier or other appliction in analog area which require good linearity.
Conclusion
Finfet appear to be the device of choice in sub 50 nm design because of their reduce short channel effect.
They seem well suited to keep us on track of moore’s law for little longer time.