16-10-2012, 03:30 PM
8086 ARCHITECTURE
[attachment=36526]
REFER DIAGRAM 1
Figure shows a block diagram of the 8086 internal architecture. As shown in the figure, the 8086 microprocessor is internally divided into two separate functional units. These are the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU fetches instructions, reads data from memory and ports, and writes data to memory and I/O ports. The EU executes instructions that have already been fetched by the BIU. The BIU and EU function independently. The BIU interfaces the 8086 to the outside world. The BIU provides all external bus operations. The BIU contains segment registers, instruction pointer, instruction queue, and address generation bus control circuitry to provide functions such as fetching and queuing of instructions, and bus control.
The BIU’s instruction queue is a First-In First-out (FIFO) group of registers in which up to six bytes of instruction code are perfected from memory ahead of time. This is done in order to speed up program execution by overlapping instruction fetch with execution. This mechanism is known as pipelining. If the queue is full and the EU does not request BIU to access memory, the BIU does not perform any bus cycle. On the other hand, if the BIU’s is not full and if it can store at least two bytes and the EU does not request it to access memory, the BIU may prefect instructions. However, if BIU is interrupted by EU for memory access while the BIU is in the process of fetching an instruction, the BIU first completes fetching and then services the EU : the queue allows the BIU to keep the EU supplied with perfected instructions without typing up the system bus. If an instruction such as Jump or subroutine call is encountered, the BIU will reset the queue and begin refilling after passing the new instruction to the EU.
REFER DIAGRAM 2
In the above SEGMENTS 0 and 1 are contiguous (adjacent) ,SEGMENTS 1 an d 2 are partially overlapped, SEGMENTS 2 and 3 are fully overlapped, and SEGMENTS 2 and 4 are disjoint.. Every segment must start on 16-byte memory boundaries.
Typical examples of values of segments should then be selected based on physical addresses starting at 0000016 , 0001016 , 0002016 , 0003016, … FF016 . A physical memory location may be mapped into (contained in) one or more logical segments. Many applications can be written to simply initialize the segment and then forget them.
REFER DIAGRAM 3
The EU decodes and executes instructions. A decoder in the EU control system translates instructions. The EU has a 16-bit ALU for performing arithmetic and logic operations.
The EU has eight 16-bit general registers. These are AX, BX, CX, DX, SP, BP, SI, and DI. The 16-bit registers AX, BX, CS, and DX can be used as two 8-bit registers (AH, AL, BH, BL, CH, CL, DH, DL). For example, the 16-bit register DX can be considered as two 8-bit registers DH (high byte of DX) and DL (low byte of DX). The general-purpose registers AX, BX, CX, and DX are named after special functions carried out by each one of them. For example, the AX is called the 16-bit accumulator while the AL is the 8-bit accumulator. The use of accumulator registers is assumed by some instructions. The Input/Output (IN or OUT) instructions always use AX or AL for inputting/outputting 16- or 8-bit data to or from and I/O port.
[attachment=36526]
REFER DIAGRAM 1
Figure shows a block diagram of the 8086 internal architecture. As shown in the figure, the 8086 microprocessor is internally divided into two separate functional units. These are the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU fetches instructions, reads data from memory and ports, and writes data to memory and I/O ports. The EU executes instructions that have already been fetched by the BIU. The BIU and EU function independently. The BIU interfaces the 8086 to the outside world. The BIU provides all external bus operations. The BIU contains segment registers, instruction pointer, instruction queue, and address generation bus control circuitry to provide functions such as fetching and queuing of instructions, and bus control.
The BIU’s instruction queue is a First-In First-out (FIFO) group of registers in which up to six bytes of instruction code are perfected from memory ahead of time. This is done in order to speed up program execution by overlapping instruction fetch with execution. This mechanism is known as pipelining. If the queue is full and the EU does not request BIU to access memory, the BIU does not perform any bus cycle. On the other hand, if the BIU’s is not full and if it can store at least two bytes and the EU does not request it to access memory, the BIU may prefect instructions. However, if BIU is interrupted by EU for memory access while the BIU is in the process of fetching an instruction, the BIU first completes fetching and then services the EU : the queue allows the BIU to keep the EU supplied with perfected instructions without typing up the system bus. If an instruction such as Jump or subroutine call is encountered, the BIU will reset the queue and begin refilling after passing the new instruction to the EU.
REFER DIAGRAM 2
In the above SEGMENTS 0 and 1 are contiguous (adjacent) ,SEGMENTS 1 an d 2 are partially overlapped, SEGMENTS 2 and 3 are fully overlapped, and SEGMENTS 2 and 4 are disjoint.. Every segment must start on 16-byte memory boundaries.
Typical examples of values of segments should then be selected based on physical addresses starting at 0000016 , 0001016 , 0002016 , 0003016, … FF016 . A physical memory location may be mapped into (contained in) one or more logical segments. Many applications can be written to simply initialize the segment and then forget them.
REFER DIAGRAM 3
The EU decodes and executes instructions. A decoder in the EU control system translates instructions. The EU has a 16-bit ALU for performing arithmetic and logic operations.
The EU has eight 16-bit general registers. These are AX, BX, CX, DX, SP, BP, SI, and DI. The 16-bit registers AX, BX, CS, and DX can be used as two 8-bit registers (AH, AL, BH, BL, CH, CL, DH, DL). For example, the 16-bit register DX can be considered as two 8-bit registers DH (high byte of DX) and DL (low byte of DX). The general-purpose registers AX, BX, CX, and DX are named after special functions carried out by each one of them. For example, the AX is called the 16-bit accumulator while the AL is the 8-bit accumulator. The use of accumulator registers is assumed by some instructions. The Input/Output (IN or OUT) instructions always use AX or AL for inputting/outputting 16- or 8-bit data to or from and I/O port.