16-10-2012, 04:46 PM
16 bit microcontroller.
[attachment=36544]
Power Management modes:
Run: CPU on, Peripherals On
Idle: CPU off, Peripherals on, current down to 5.8 uA
Sleep: CPU off, Peripherals off , current down to 0.1 uA
Peripheral Highlights
- High current sink/source up to 25mA
- Three programmable external interrupts
- Four input change interrupts
- Enhanced Capture/Compare/PWM (ECCP) module
- Enhanced Addressable USART module
- 10-bit, up to 13-channel Analog-to-Digital Converter module
- 3 16-bit times, 1 8 bit times
Memory Detail
- Program Memory Flash 32 K bytes (16384 single word instruction)
- Data Memory SRAM 1536 bytes
- IO pins 36
- 13 10-bit A/D channel
IP Ports
Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
Each port has three registers for its operation. These registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the device)
• LAT register (output latch)
The Data Latch (LAT register) is useful for read-modify write operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 10-1.
PORTA is a 8-bit wide, bidirectional port. Data direction register is set by TRISA bit.
- TRISA = 1- PORTA becomes input port. (i.e put the corresponding output driver in a high-impedance mode).
- TRISA = 0- PORTA becomes output port. (i.e put the contents of the output latch on the selected pin)
Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch.
The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA.
EUSART: (Enhanced Universal Synchronous Asynchronous Receiver Transmitter).
The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit.
[attachment=36544]
Power Management modes:
Run: CPU on, Peripherals On
Idle: CPU off, Peripherals on, current down to 5.8 uA
Sleep: CPU off, Peripherals off , current down to 0.1 uA
Peripheral Highlights
- High current sink/source up to 25mA
- Three programmable external interrupts
- Four input change interrupts
- Enhanced Capture/Compare/PWM (ECCP) module
- Enhanced Addressable USART module
- 10-bit, up to 13-channel Analog-to-Digital Converter module
- 3 16-bit times, 1 8 bit times
Memory Detail
- Program Memory Flash 32 K bytes (16384 single word instruction)
- Data Memory SRAM 1536 bytes
- IO pins 36
- 13 10-bit A/D channel
IP Ports
Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
Each port has three registers for its operation. These registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the device)
• LAT register (output latch)
The Data Latch (LAT register) is useful for read-modify write operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 10-1.
PORTA is a 8-bit wide, bidirectional port. Data direction register is set by TRISA bit.
- TRISA = 1- PORTA becomes input port. (i.e put the corresponding output driver in a high-impedance mode).
- TRISA = 0- PORTA becomes output port. (i.e put the contents of the output latch on the selected pin)
Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch.
The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA.
EUSART: (Enhanced Universal Synchronous Asynchronous Receiver Transmitter).
The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit.