19-10-2012, 05:41 PM
8086 Architecture Details
[attachment=36767]
BIU (Bus Interface Unit)
It provides a full 16 bit bidirectional data bus and 20 bit address bus.
The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.
FETCH AND EXECUTE
Although the 8086/88 still functions as a stored program computer, organization of the CPU into a separate BIU and EU allows the fetch and execute cycles to overlap.
To see this, consider what happens when the 8086 or 8088 is first started.
1. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the selected byte or word to be read into the BIU.
2. Register IP is incremented by 1 to prepare for the next instruction fetch.
Source Index (SI)
String instructions can be used to transfer data blocks from source memory locations to the destinations memory locations.
For reading from the source memory locations, µp will select source memory location by transferring physical address of the source.
To generate physical address of source, microprocessor will take base address from DS register and effective address from SI register (DS:SI).
Segment registers and Instruction Pointer (IP)
You should realize that the concept of the segmented memory is a unique one.
Older-generation microprocessors such as the 8-bit 8086 or Z-80 could access only one 64K-byte segment.
This mean that the programs instruction, data and subroutine stack all had to share the same memory.
This limited the amount of memory available for the program itself and led to disaster if the stack should happen to overwrite the data or program areas
[attachment=36767]
BIU (Bus Interface Unit)
It provides a full 16 bit bidirectional data bus and 20 bit address bus.
The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.
FETCH AND EXECUTE
Although the 8086/88 still functions as a stored program computer, organization of the CPU into a separate BIU and EU allows the fetch and execute cycles to overlap.
To see this, consider what happens when the 8086 or 8088 is first started.
1. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the selected byte or word to be read into the BIU.
2. Register IP is incremented by 1 to prepare for the next instruction fetch.
Source Index (SI)
String instructions can be used to transfer data blocks from source memory locations to the destinations memory locations.
For reading from the source memory locations, µp will select source memory location by transferring physical address of the source.
To generate physical address of source, microprocessor will take base address from DS register and effective address from SI register (DS:SI).
Segment registers and Instruction Pointer (IP)
You should realize that the concept of the segmented memory is a unique one.
Older-generation microprocessors such as the 8-bit 8086 or Z-80 could access only one 64K-byte segment.
This mean that the programs instruction, data and subroutine stack all had to share the same memory.
This limited the amount of memory available for the program itself and led to disaster if the stack should happen to overwrite the data or program areas