10-11-2012, 04:53 PM
PRACTICAL LOW-COST CPL IMPLEMENTATIONS OF THRESHOLD LOGIC FUNCTIONS
[attachment=38998]
ABSTRACT
This paper gives the rationale for the Complementary Pass-Transistor
Logic (CPL) implementation of threshold gates for the
design of complex logic functions. The interesting low-power
properties of CPL circuits and the efficiency with which a broad
class of functions can be implemented by threshold functions
make the proposed methodology extremely useful. A number of
implementation examples are given which illustrate the feasibility
and versatility of the proposed technique and its potential as a lowcost
design technique for CMOS technologies. Simulation results
confirm our expectations.
INTRODUCTION
Circuit design based on threshold gates has been considered for
many years an alternative to the traditional logic gate design procedure
because of their acknowledged power. The power of the
threshold gate design style lies in the intrinsic complex functions
implemented by such gates, which allows for realizations that require
less threshold gates than standard logic gates [1]. More recently,
a number of theoretical results show that polynomial-size,
bounded level networks of threshold gates can implement functions
that require unbounded level networks of standard logic gates [2-
4]. In particular, important functions like multiple-addition, multiplication,
division, or sorting can be implemented by polynomialsize
threshold circuits of small constant depth. Threshold gate networks
have also been found useful in modeling nerve nets and brain
organization, and with variable threshold (or weights) values they
have been used to model learning systems, adaptive systems, selfrepairing
systems, pattern recognition systems, etc.
CPL-BASED THRESHOLD GATES
In this section we will prove that the steering logic structure proposed
in the previous section can be easily transformed into a
Complementary Pass-Transistor Logic (CPL) structure. The main
concepts behind CPL are the use of complementary input/outputs,
an nMOS pass-transistor logic network, and CMOS output inverters.
Additionally, a pMOS latch can be added to decrease static
power consumption and for swing restoration, as opposed to the
conventional pull-up function. To obtain these characteristics, we
will consider the circuits shown in Figure 6, which can be considered
a “dual” of the other once because they are obtained by simply
exchanging logic 0’s and logic 1’s.
CONCLUSIONS
A design methodology for implementing CPL-based threshold
gates has been presented. It provides an easy and systematic way
to build threshold functions. Implementation of threshold gates by
the circuits thus obtained does not depend on the weight associated
to each input. This is a distinguishing characteristic which differentiates
these implementations from others which have been
reported. Several examples of circuit implementations have been
presented which take advantage of both the CPL logic design style
and the power of the threshold gate based paradigm. Experimental
results confirm the suitability of the proposed methodology.
[attachment=38998]
ABSTRACT
This paper gives the rationale for the Complementary Pass-Transistor
Logic (CPL) implementation of threshold gates for the
design of complex logic functions. The interesting low-power
properties of CPL circuits and the efficiency with which a broad
class of functions can be implemented by threshold functions
make the proposed methodology extremely useful. A number of
implementation examples are given which illustrate the feasibility
and versatility of the proposed technique and its potential as a lowcost
design technique for CMOS technologies. Simulation results
confirm our expectations.
INTRODUCTION
Circuit design based on threshold gates has been considered for
many years an alternative to the traditional logic gate design procedure
because of their acknowledged power. The power of the
threshold gate design style lies in the intrinsic complex functions
implemented by such gates, which allows for realizations that require
less threshold gates than standard logic gates [1]. More recently,
a number of theoretical results show that polynomial-size,
bounded level networks of threshold gates can implement functions
that require unbounded level networks of standard logic gates [2-
4]. In particular, important functions like multiple-addition, multiplication,
division, or sorting can be implemented by polynomialsize
threshold circuits of small constant depth. Threshold gate networks
have also been found useful in modeling nerve nets and brain
organization, and with variable threshold (or weights) values they
have been used to model learning systems, adaptive systems, selfrepairing
systems, pattern recognition systems, etc.
CPL-BASED THRESHOLD GATES
In this section we will prove that the steering logic structure proposed
in the previous section can be easily transformed into a
Complementary Pass-Transistor Logic (CPL) structure. The main
concepts behind CPL are the use of complementary input/outputs,
an nMOS pass-transistor logic network, and CMOS output inverters.
Additionally, a pMOS latch can be added to decrease static
power consumption and for swing restoration, as opposed to the
conventional pull-up function. To obtain these characteristics, we
will consider the circuits shown in Figure 6, which can be considered
a “dual” of the other once because they are obtained by simply
exchanging logic 0’s and logic 1’s.
CONCLUSIONS
A design methodology for implementing CPL-based threshold
gates has been presented. It provides an easy and systematic way
to build threshold functions. Implementation of threshold gates by
the circuits thus obtained does not depend on the weight associated
to each input. This is a distinguishing characteristic which differentiates
these implementations from others which have been
reported. Several examples of circuit implementations have been
presented which take advantage of both the CPL logic design style
and the power of the threshold gate based paradigm. Experimental
results confirm the suitability of the proposed methodology.