10-11-2012, 05:09 PM
Serial programmer / IC Burner for 8051 Microcontrollers
[attachment=39009]
In-System Programming (abbreviated ISP) is the
ability of some programmable logic devices,
microcontrollers, and other programmable
electronic chips to be programmed while installed
in a complete system, rather than requiring the chip
to be programmed prior to installing it into the
system. The primary advantage of this feature is that
it allows manufacturers of electronic devices to
integrate programming and testing into a single
production phase, rather than requiring a separate
programming stage prior to assembling the system.
This may allow manufacturers to program the chips
in their own system's production line instead of
buying preprogrammed chips from a manufacturer
or distributor, making it feasible to apply code or
design changes in the middle of a production run.
NXP P89V51RD2 microcontroller can be
programmed using this IC Burner. The P89V51RD2
is an 80C51 microcontroller with 64 kB Flash and
1024 bytes of data RAM. A key feature of the
P89V51RD2 is its X2 mode option. The design
engineer can choose to run the application with the
conventional 80C51 clock rate (12 clocks per
machine cycle) or select the X2 mode (6 clocks per
machine cycle) to achieve twice the throughput at
the same clock frequency. Another way to benefit
from this feature is to keep the same performance
by reducing the clock frequency by half, thus
dramatically reducing the EMI. The Flash program
memory supports both parallel programming and
in serial In-System Programming (ISP).
Memory organization
The device has separate address spaces for
program and data memory.
Flash program memory
There are two internal flash memory blocks in the
device. Block 0 has 64 kbytes and contains the
user's code. Block 1 contains the Philips-provided
ISP/IAP routines and may be enabled such that it
overlays the first 8 kbytes of the user code memory.
The 64 kB Block 0 is organized as 512 sectors,
each sector consists of 128 bytes. Access to the IAP
routines may be enabled by clearing the BSEL bit in
the FCF register. However, caution must be taken
when dynamically changing the BSEL bit. Since this
will cause different physical memory to be mapped
to the logical program address space, the user must
avoid clearing the BSEL bit when executing user
code within the address range 0000H to 1FFFH.
[attachment=39009]
In-System Programming (abbreviated ISP) is the
ability of some programmable logic devices,
microcontrollers, and other programmable
electronic chips to be programmed while installed
in a complete system, rather than requiring the chip
to be programmed prior to installing it into the
system. The primary advantage of this feature is that
it allows manufacturers of electronic devices to
integrate programming and testing into a single
production phase, rather than requiring a separate
programming stage prior to assembling the system.
This may allow manufacturers to program the chips
in their own system's production line instead of
buying preprogrammed chips from a manufacturer
or distributor, making it feasible to apply code or
design changes in the middle of a production run.
NXP P89V51RD2 microcontroller can be
programmed using this IC Burner. The P89V51RD2
is an 80C51 microcontroller with 64 kB Flash and
1024 bytes of data RAM. A key feature of the
P89V51RD2 is its X2 mode option. The design
engineer can choose to run the application with the
conventional 80C51 clock rate (12 clocks per
machine cycle) or select the X2 mode (6 clocks per
machine cycle) to achieve twice the throughput at
the same clock frequency. Another way to benefit
from this feature is to keep the same performance
by reducing the clock frequency by half, thus
dramatically reducing the EMI. The Flash program
memory supports both parallel programming and
in serial In-System Programming (ISP).
Memory organization
The device has separate address spaces for
program and data memory.
Flash program memory
There are two internal flash memory blocks in the
device. Block 0 has 64 kbytes and contains the
user's code. Block 1 contains the Philips-provided
ISP/IAP routines and may be enabled such that it
overlays the first 8 kbytes of the user code memory.
The 64 kB Block 0 is organized as 512 sectors,
each sector consists of 128 bytes. Access to the IAP
routines may be enabled by clearing the BSEL bit in
the FCF register. However, caution must be taken
when dynamically changing the BSEL bit. Since this
will cause different physical memory to be mapped
to the logical program address space, the user must
avoid clearing the BSEL bit when executing user
code within the address range 0000H to 1FFFH.