10-11-2012, 05:20 PM
EE25M Introduction to microprocessors
[attachment=39011]
Architecture of the PIC microcontroller
The history of the PIC series of microcontrollers started in in 1965, when General Instruments (GI)
formed a Microelectronics Division, and used this division to generate some of the earliest viable
EPROM and EEPROM memory architectures. GI also made a 16 bit microprocessor, called the
CP1600, in the early 1970s. While this was a reasonable microprocessor, it was not particularly
good at handling I/O. Therefore, around 1975, GI designed a Peripheral Interface Controller (or
PIC for short) for some very speci¯c applications where good I/O handling was needed. It was
designed to be very fast since it was I/O handling for a 16 bit machine, but it did not need a
large amount of functionality, so its microcoded instruction set was small. Its architecture was
substantially the PIC16C5x architecture of today. The market for the PIC remained small for
the next few years. During the early 1980s, GI restructured their business to concentrate more
on their core activity which was power semiconductors. As a result of the restructuring, the GI
Microelectronics Division became GI Microelectronics Inc (a wholly owned subsidiary) which, in
1985, was ¯nally sold to venture capital investors. The sale included the fabrication plant in
Chandler, Arizona. The new owners decided to concentrate on the PICs, the serial and parallel
EEPROMs and the parallel EPROMs. A decision was later taken to start a new company, named
Arizona MicroChip Technology, with embedded control as its di®erentiator from the rest of the
industry. As part of this strategy, the PIC family was redesigned to use one of the other things
that the °edgling company was good at, i.e. EPROM. With the addition of CMOS technology and
erasable EPROM program memory the PIC family, as we know it, was born.
Memory Layout
The PIC16F877 has 8K £ 14-bit words of Flash program memory, 368 bytes of data RAM, 256
bytes of data EEPROM and an 8-level x 13 bit wide hardware stack.
The Program Counter (PC) is 13 bits wide, thus making it possible to access all 8K x 14 addresses.
The low byte is the PCL (Program Counter Low byte) register which is a readable and writable
register. The high byte of the PC (PC<12:8>) is not directly readable or writable and comes from
the PCLATH (Program Counter LATch High) register. The PCLATH register is a holding register
for the PC<12:8>. The contents of the PCLATH are transferred to the upper byte of the program
counter when the PC is loaded with a new value. Although the PC is capable of addressing the entire
program memory space, conceptually the program memory is represented by four banks of 2K £
14-bit words. Banking is necessary since there are only 11 bits for the address in the instruction
word for a call or goto. The other two bits are obtained from the top two bits of PCLATH (i.e.
PCLATH<4:3>). This means that the user must set those extra bits in PCLATH before branching
out of the 2K bank that contains the current instruction. Within the program memory space, the
reset vector (location to go to on reset) is at 0000h and the interrupt vector (location to go to on
interrupt) is at 0004h.
[attachment=39011]
Architecture of the PIC microcontroller
The history of the PIC series of microcontrollers started in in 1965, when General Instruments (GI)
formed a Microelectronics Division, and used this division to generate some of the earliest viable
EPROM and EEPROM memory architectures. GI also made a 16 bit microprocessor, called the
CP1600, in the early 1970s. While this was a reasonable microprocessor, it was not particularly
good at handling I/O. Therefore, around 1975, GI designed a Peripheral Interface Controller (or
PIC for short) for some very speci¯c applications where good I/O handling was needed. It was
designed to be very fast since it was I/O handling for a 16 bit machine, but it did not need a
large amount of functionality, so its microcoded instruction set was small. Its architecture was
substantially the PIC16C5x architecture of today. The market for the PIC remained small for
the next few years. During the early 1980s, GI restructured their business to concentrate more
on their core activity which was power semiconductors. As a result of the restructuring, the GI
Microelectronics Division became GI Microelectronics Inc (a wholly owned subsidiary) which, in
1985, was ¯nally sold to venture capital investors. The sale included the fabrication plant in
Chandler, Arizona. The new owners decided to concentrate on the PICs, the serial and parallel
EEPROMs and the parallel EPROMs. A decision was later taken to start a new company, named
Arizona MicroChip Technology, with embedded control as its di®erentiator from the rest of the
industry. As part of this strategy, the PIC family was redesigned to use one of the other things
that the °edgling company was good at, i.e. EPROM. With the addition of CMOS technology and
erasable EPROM program memory the PIC family, as we know it, was born.
Memory Layout
The PIC16F877 has 8K £ 14-bit words of Flash program memory, 368 bytes of data RAM, 256
bytes of data EEPROM and an 8-level x 13 bit wide hardware stack.
The Program Counter (PC) is 13 bits wide, thus making it possible to access all 8K x 14 addresses.
The low byte is the PCL (Program Counter Low byte) register which is a readable and writable
register. The high byte of the PC (PC<12:8>) is not directly readable or writable and comes from
the PCLATH (Program Counter LATch High) register. The PCLATH register is a holding register
for the PC<12:8>. The contents of the PCLATH are transferred to the upper byte of the program
counter when the PC is loaded with a new value. Although the PC is capable of addressing the entire
program memory space, conceptually the program memory is represented by four banks of 2K £
14-bit words. Banking is necessary since there are only 11 bits for the address in the instruction
word for a call or goto. The other two bits are obtained from the top two bits of PCLATH (i.e.
PCLATH<4:3>). This means that the user must set those extra bits in PCLATH before branching
out of the 2K bank that contains the current instruction. Within the program memory space, the
reset vector (location to go to on reset) is at 0000h and the interrupt vector (location to go to on
interrupt) is at 0004h.