12-11-2012, 03:55 PM
Transactions Briefs
[attachment=39111]
Abstract
Weighted pseudorandom built-in self test (BIST) schemes
have been utilized in order to drive down the number of vectors to achieve
complete fault coverage in BIST applications. Weighted sets comprising
three weights, namely 0, 1, and 0.5 have been successfully utilized so far
for test pattern generation, since they result in both low testing time and
low consumed power. In this paper an accumulator-based 3-weight test
pattern generation scheme is presented; the proposed scheme generates set
of patterns with weights 0, 0.5, and 1. Since accumulators are commonly
found in current VLSI chips, this scheme can be efficiently utilized to drive
down the hardware of BIST pattern generation, as well. Comparisons with
previously presented schemes indicate that the proposed scheme compares
favorably with respect to the required hardware.
INTRODUCTION
Pseudorandom built-in self test (BIST) generators have been widely
utilized to test integrated circuits and systems. The arsenal of pseudorandom
generators includes, among others, linear feedback shift registers
(LFSRs) [1], cellular automata [2], and accumulators driven by
a constant value [3]. For circuits with hard-to-detect faults, a large
number of random patterns have to be generated before high fault coverage
is achieved. Therefore, weighted pseudorandom techniques have
been proposed where inputs are biased by changing the probability of
a “0” or a “1” on a given input from 0.5 (for pure pseudorandom tests)
to some other value [10], [15].
Weighted random pattern generation methods relying on a single
weight assignment usually fail to achieve complete fault coverage
using a reasonable number of test patterns since, although the weights
are computed to be suitable for most faults, some faults may require
long test sequences to be detected with these weight assignments
if they do not match their activation and propagation requirements.
Multiple weight assignments have been suggested for the case that
different faults require different biases of the input combinations applied
to the circuit, to ensure that a relatively small number of patterns
can detect all faults [4]. Approaches to derive weight assignments for
given deterministic tests are attractive since they have the potential to
allow complete coverage with a significantly smaller number of test
patterns [10].
COMPARISONS
In this section, we shall perform comparisons in three directions.
In Section IV-A, we shall compare the proposed scheme with the accumulator-
based 3-weight generation scheme that has been proposed
in [11]. In Section IV-B, we shall compare the proposed scheme with
the 3-weight scan schemes that have been proposed in [5] and [8].
In Section IV-C, in order to demonstrate the applicability of the proposed
scheme we shall compare the proposed scheme with the accumulator-
based test pattern generation scheme proposed in [22].
A. Comparisons With [11]
The number of test patterns applied by [11] and the proposed scheme
is the same, since the test application algorithms that have been invented
and applied by previous researchers, e.g., [5], [8], [9] can be
equally well applied with both implementations. Therefore, the comparison
will be performed with respect to: 1) the hardware overhead
and 2) the impact on the timing characteristics of the adder of the accumulator.
Comparisons With Scan-Based Schemes [5], [8]
Since the test application algorithms that have been invented and applied
by [5], [8], and [9] can be equally well applied with the proposed
scheme, test application time is similar to that reported there. Therefore,
the comparison will be performed with respect to hardware overhead.
In the 3-weight pattern generation scheme proposed by Pomeranz
and Reddy in [5] the scan chain is driven by the output of a linear feedback
shift register (LFSR). Logic is inserted between the scan chain
and the CUT inputs to fix the outputs to the required weight (0, 0.5, or
1). In order to implement the scheme [5], a scan-structure is assumed.
Furthermore, an LFSR required to feed the pseudorandom inputs to
the scan inputs is implemented (the number of LFSR stages is ,
where is the number of scan cells), as well as a scan counter, common
to all scan schemes. A number of 3-gate modules is required for every
required weighted input (in [5, Table V], the hardware overhead is calculated
for the ISCAS’85 benchmarks).
CONCLUSION
We have presented an accumulator-based 3-weight (0, 0.5, and 1)
test-per-clock generation scheme, which can be utilized to efficiently
generate weighted patterns without altering the structure of the adder.
Comparisons with a previously proposed accumulator-based
3-weight pattern generation technique [11] indicate that the hardware
overhead of the proposed scheme is lower (
[attachment=39111]
Abstract
Weighted pseudorandom built-in self test (BIST) schemes
have been utilized in order to drive down the number of vectors to achieve
complete fault coverage in BIST applications. Weighted sets comprising
three weights, namely 0, 1, and 0.5 have been successfully utilized so far
for test pattern generation, since they result in both low testing time and
low consumed power. In this paper an accumulator-based 3-weight test
pattern generation scheme is presented; the proposed scheme generates set
of patterns with weights 0, 0.5, and 1. Since accumulators are commonly
found in current VLSI chips, this scheme can be efficiently utilized to drive
down the hardware of BIST pattern generation, as well. Comparisons with
previously presented schemes indicate that the proposed scheme compares
favorably with respect to the required hardware.
INTRODUCTION
Pseudorandom built-in self test (BIST) generators have been widely
utilized to test integrated circuits and systems. The arsenal of pseudorandom
generators includes, among others, linear feedback shift registers
(LFSRs) [1], cellular automata [2], and accumulators driven by
a constant value [3]. For circuits with hard-to-detect faults, a large
number of random patterns have to be generated before high fault coverage
is achieved. Therefore, weighted pseudorandom techniques have
been proposed where inputs are biased by changing the probability of
a “0” or a “1” on a given input from 0.5 (for pure pseudorandom tests)
to some other value [10], [15].
Weighted random pattern generation methods relying on a single
weight assignment usually fail to achieve complete fault coverage
using a reasonable number of test patterns since, although the weights
are computed to be suitable for most faults, some faults may require
long test sequences to be detected with these weight assignments
if they do not match their activation and propagation requirements.
Multiple weight assignments have been suggested for the case that
different faults require different biases of the input combinations applied
to the circuit, to ensure that a relatively small number of patterns
can detect all faults [4]. Approaches to derive weight assignments for
given deterministic tests are attractive since they have the potential to
allow complete coverage with a significantly smaller number of test
patterns [10].
COMPARISONS
In this section, we shall perform comparisons in three directions.
In Section IV-A, we shall compare the proposed scheme with the accumulator-
based 3-weight generation scheme that has been proposed
in [11]. In Section IV-B, we shall compare the proposed scheme with
the 3-weight scan schemes that have been proposed in [5] and [8].
In Section IV-C, in order to demonstrate the applicability of the proposed
scheme we shall compare the proposed scheme with the accumulator-
based test pattern generation scheme proposed in [22].
A. Comparisons With [11]
The number of test patterns applied by [11] and the proposed scheme
is the same, since the test application algorithms that have been invented
and applied by previous researchers, e.g., [5], [8], [9] can be
equally well applied with both implementations. Therefore, the comparison
will be performed with respect to: 1) the hardware overhead
and 2) the impact on the timing characteristics of the adder of the accumulator.
Comparisons With Scan-Based Schemes [5], [8]
Since the test application algorithms that have been invented and applied
by [5], [8], and [9] can be equally well applied with the proposed
scheme, test application time is similar to that reported there. Therefore,
the comparison will be performed with respect to hardware overhead.
In the 3-weight pattern generation scheme proposed by Pomeranz
and Reddy in [5] the scan chain is driven by the output of a linear feedback
shift register (LFSR). Logic is inserted between the scan chain
and the CUT inputs to fix the outputs to the required weight (0, 0.5, or
1). In order to implement the scheme [5], a scan-structure is assumed.
Furthermore, an LFSR required to feed the pseudorandom inputs to
the scan inputs is implemented (the number of LFSR stages is ,
where is the number of scan cells), as well as a scan counter, common
to all scan schemes. A number of 3-gate modules is required for every
required weighted input (in [5, Table V], the hardware overhead is calculated
for the ISCAS’85 benchmarks).
CONCLUSION
We have presented an accumulator-based 3-weight (0, 0.5, and 1)
test-per-clock generation scheme, which can be utilized to efficiently
generate weighted patterns without altering the structure of the adder.
Comparisons with a previously proposed accumulator-based
3-weight pattern generation technique [11] indicate that the hardware
overhead of the proposed scheme is lower (