13-11-2012, 05:10 PM
FUTURE PROSPECTS FOR CMOS ACTIVE PIXEL SENSORS
[attachment=39299]
CMOS APS OVERVIEW
• Second generation solid-state image sensor technology
• Retains nearly all the performance of a CCD
• Unique advantages of CMOS APS:
– Ultra low power system, >100x less than CCD system
– Highly integrated on-chip electronics reduces component count
– Commercial CMOS technology leverage
– Don’t need a dedicated CCD fab line to make sensors ($$)
– Random access and window-of-interest pixel readout
– Standard 5 volt (or 3.3 volt) operation
– Faster readout
– Radiation hard
– Larger format arrays
• Strong commercial, biomedical, defense, and space applications
PROBLEMS WITH CCDs
• Charge-coupled devices (CCDs) invented around 1970.
– Uses repeated lateral charge transfer to readout image.
• Need for nearly perfect charge transfer efficiency is Achilles’ heel.
– Requires specialized fabrication process so not 100% CMOS
compatible.
– Requires numerous different voltages to achieve good performance
– Susceptible to bulk radiation damage so radiation “soft”
• CCDs are large capacitance devices so on-chip drive circuits difficult to
implement.
– Excessive power dissipation
– Hot electron photon emission
– Process incompatibility
• On-chip signal processing (e.g. ADC) difficult to implement in CCD
technology.
CONSEQUENCES OF TECHNOLOGY SCALING
DARK CURRENT
• “OFF” Currents increase
– shorter length
– lower threshold voltage
• Higher doping will increase pn junction leakage currents
• Better contamination control will lower dark current
• Gate oxide tunneling current not too important
– current scales with electric field (i.e. signal charge)
– tunneling current looks mostly like majority carrier current
– minority carrier tunneling will lead to “anti-blooming effect”
• Gate-induced leakage current a concern in higher doped junctions
• Hot carrier effects not expected to increase due to voltage scaling
[attachment=39299]
CMOS APS OVERVIEW
• Second generation solid-state image sensor technology
• Retains nearly all the performance of a CCD
• Unique advantages of CMOS APS:
– Ultra low power system, >100x less than CCD system
– Highly integrated on-chip electronics reduces component count
– Commercial CMOS technology leverage
– Don’t need a dedicated CCD fab line to make sensors ($$)
– Random access and window-of-interest pixel readout
– Standard 5 volt (or 3.3 volt) operation
– Faster readout
– Radiation hard
– Larger format arrays
• Strong commercial, biomedical, defense, and space applications
PROBLEMS WITH CCDs
• Charge-coupled devices (CCDs) invented around 1970.
– Uses repeated lateral charge transfer to readout image.
• Need for nearly perfect charge transfer efficiency is Achilles’ heel.
– Requires specialized fabrication process so not 100% CMOS
compatible.
– Requires numerous different voltages to achieve good performance
– Susceptible to bulk radiation damage so radiation “soft”
• CCDs are large capacitance devices so on-chip drive circuits difficult to
implement.
– Excessive power dissipation
– Hot electron photon emission
– Process incompatibility
• On-chip signal processing (e.g. ADC) difficult to implement in CCD
technology.
CONSEQUENCES OF TECHNOLOGY SCALING
DARK CURRENT
• “OFF” Currents increase
– shorter length
– lower threshold voltage
• Higher doping will increase pn junction leakage currents
• Better contamination control will lower dark current
• Gate oxide tunneling current not too important
– current scales with electric field (i.e. signal charge)
– tunneling current looks mostly like majority carrier current
– minority carrier tunneling will lead to “anti-blooming effect”
• Gate-induced leakage current a concern in higher doped junctions
• Hot carrier effects not expected to increase due to voltage scaling