26-11-2012, 11:43 AM
82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
[attachment=41117]
The Intel 82C55A is a high-performance, CHMOS version of the industry standard 8255A general purpose
programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides
24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation.
The 82C55A is pin compatible with the NMOS 8255A and 8255A-5.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In
MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used
for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration.
The 82C55A is fabricated on Intel's advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent NMOS product. The 82C55A is available in 40-pin
DIP and 44-pin plastic leaded chip carrier (PLCC) packages.
82C55A FUNCTIONAL DESCRIPTION
General
The 82C55A is a programmable peripheral interface
device designed for use in Intel microcomputer systems.
Its function is that of a general purpose I/O
component to interface peripheral equipment to the
microcomputer system bus. The functional configuration
of the 82C55A is programmed by the system
software so that normally no external logic is necessary
to interface peripheral devices or structures.
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is
transmitted or received by the buffer upon execution
of input or output instructions by the CPU. Control
words and status information are also transferred
through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the
internal and external transfers of both Data and
Control or Status words. It accepts inputs from the
CPU Address and Control busses and in turn, issues
commands to both of the Control Groups.
Group A and Group B Controls
The functional configuration of each port is programmed
by the systems software. In essence, the
CPU ``outputs'' a control word to the 82C55A. The
control word contains information such as ``mode'',
``bit set'', ``bit reset'', etc., that initializes the functional
configuration of the 82C55A.
82C55A OPERATIONAL DESCRIPTION
Mode Selection
There are three basic modes of operation that can
be selected by the system software:
Mode 0 Ð Basic input/output
Mode 1 Ð Strobed Input/output
Mode 2 Ð Bi-directional Bus
When the reset input goes ``high'' all ports will be set
to the input mode with all 24 port lines held at a logic
``one'' level by the internal bus hold devices (see
Figure 4 Note). After the reset is removed the
82C55A can remain in the input mode with no additional
initialization required. This eliminates the need
for pullup or pulldown devices in ``all CMOS'' designs.
During the execution of the system program,
any of the other modes may be selected by using a
single output instruction. This allows a single
82C55A to service a variety of peripheral devices
with a simple software maintenance routine.
The modes for Port A and Port B can be separately
defined, while Port C is divided into two portions as
required by the Port A and Port B definitions. All of
the output registers, including the status flip-flops,
will be reset whenever the mode is changed. Modes
may be combined so that their functional definition
can be ``tailored'' to almost any I/O structure. For
instance; Group B can be programmed in Mode 0 to
monitor simple switch closings or display computational
results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an
interrupt-driven basis.
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset
using a single OUTput instruction. This feature reduces
software requirements in Control-based applications.
When Port C is being used as status/control for Port
A or B, these bits can be set or reset by using the Bit
Set/Reset operation just as if they were data output
ports.
Current Drive Capability
Any output on Port A, B or C can sink or source 2.5
mA. This feature allows the 82C55A to directly drive
Darlington type drivers and high-voltage displays
that require such sink or source current.
Reading Port C Status
In Mode 0, Port C transfers data to or from the peripheral
device. When the 82C55A is programmed to
function in Modes 1 or 2, Port C generates or accepts
``hand-shaking'' signals with the peripheral device.
Reading the contents of Port C allows the programmer
to test or verify the ``status'' of each peripheral
device and change the program flow accordingly.
There is no special instruction to read the status information
from Port C. A normal read operation of
Port C is executed to perform this function.
[attachment=41117]
The Intel 82C55A is a high-performance, CHMOS version of the industry standard 8255A general purpose
programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides
24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation.
The 82C55A is pin compatible with the NMOS 8255A and 8255A-5.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In
MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used
for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration.
The 82C55A is fabricated on Intel's advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent NMOS product. The 82C55A is available in 40-pin
DIP and 44-pin plastic leaded chip carrier (PLCC) packages.
82C55A FUNCTIONAL DESCRIPTION
General
The 82C55A is a programmable peripheral interface
device designed for use in Intel microcomputer systems.
Its function is that of a general purpose I/O
component to interface peripheral equipment to the
microcomputer system bus. The functional configuration
of the 82C55A is programmed by the system
software so that normally no external logic is necessary
to interface peripheral devices or structures.
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is
transmitted or received by the buffer upon execution
of input or output instructions by the CPU. Control
words and status information are also transferred
through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the
internal and external transfers of both Data and
Control or Status words. It accepts inputs from the
CPU Address and Control busses and in turn, issues
commands to both of the Control Groups.
Group A and Group B Controls
The functional configuration of each port is programmed
by the systems software. In essence, the
CPU ``outputs'' a control word to the 82C55A. The
control word contains information such as ``mode'',
``bit set'', ``bit reset'', etc., that initializes the functional
configuration of the 82C55A.
82C55A OPERATIONAL DESCRIPTION
Mode Selection
There are three basic modes of operation that can
be selected by the system software:
Mode 0 Ð Basic input/output
Mode 1 Ð Strobed Input/output
Mode 2 Ð Bi-directional Bus
When the reset input goes ``high'' all ports will be set
to the input mode with all 24 port lines held at a logic
``one'' level by the internal bus hold devices (see
Figure 4 Note). After the reset is removed the
82C55A can remain in the input mode with no additional
initialization required. This eliminates the need
for pullup or pulldown devices in ``all CMOS'' designs.
During the execution of the system program,
any of the other modes may be selected by using a
single output instruction. This allows a single
82C55A to service a variety of peripheral devices
with a simple software maintenance routine.
The modes for Port A and Port B can be separately
defined, while Port C is divided into two portions as
required by the Port A and Port B definitions. All of
the output registers, including the status flip-flops,
will be reset whenever the mode is changed. Modes
may be combined so that their functional definition
can be ``tailored'' to almost any I/O structure. For
instance; Group B can be programmed in Mode 0 to
monitor simple switch closings or display computational
results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an
interrupt-driven basis.
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset
using a single OUTput instruction. This feature reduces
software requirements in Control-based applications.
When Port C is being used as status/control for Port
A or B, these bits can be set or reset by using the Bit
Set/Reset operation just as if they were data output
ports.
Current Drive Capability
Any output on Port A, B or C can sink or source 2.5
mA. This feature allows the 82C55A to directly drive
Darlington type drivers and high-voltage displays
that require such sink or source current.
Reading Port C Status
In Mode 0, Port C transfers data to or from the peripheral
device. When the 82C55A is programmed to
function in Modes 1 or 2, Port C generates or accepts
``hand-shaking'' signals with the peripheral device.
Reading the contents of Port C allows the programmer
to test or verify the ``status'' of each peripheral
device and change the program flow accordingly.
There is no special instruction to read the status information
from Port C. A normal read operation of
Port C is executed to perform this function.