29-11-2012, 03:51 PM
ARM 11
[attachment=41695]
history
ARM 11 is the first implementation of the ARMv6 instruction set architecture
It is the base for all family of ARM 11 cores
The key objective in developing ARM 11 microarchitecture was to deliver high performance and low power consumption together with low price
ARM 11 has impact on wide variety of applications in wireless, consumer, networking and automotive segments
Performance
Superior performance of ARM 11 cores is possible because of ARMv6 architecture
ARMv6 delivers superior performance trough:
Media processing extensions
Improved cache architecture
Improved exception and interrupt handling
Unaligned and mixed – endian data support
features
ARM 11 is Reduced Instruction Set Computer (RISC) and it incorporates following features:
Large uniform register file
Load/store architecture where data – processing operations only operate on register contents and not directly on memory
Simple addressing modes with all load/store addresses being determined from register contents and instruction fields only
registers
ARM 11 has 31 general purpose 32-bit registers and 6 status registers
At any of times only 16 of these registers are visible and the others are used to speed up exception processing.
3 of those 16 visible registers have special roles (stack pointer, link register and program counter).
Instruction set
ARM 11 instruction set can be divided in 6 classes of instructions:
Branch instructions
Data processing instructions
Status register transfer instructions
Load and store instructions
Coprocessors instructions
Exception generating instructions
[attachment=41695]
history
ARM 11 is the first implementation of the ARMv6 instruction set architecture
It is the base for all family of ARM 11 cores
The key objective in developing ARM 11 microarchitecture was to deliver high performance and low power consumption together with low price
ARM 11 has impact on wide variety of applications in wireless, consumer, networking and automotive segments
Performance
Superior performance of ARM 11 cores is possible because of ARMv6 architecture
ARMv6 delivers superior performance trough:
Media processing extensions
Improved cache architecture
Improved exception and interrupt handling
Unaligned and mixed – endian data support
features
ARM 11 is Reduced Instruction Set Computer (RISC) and it incorporates following features:
Large uniform register file
Load/store architecture where data – processing operations only operate on register contents and not directly on memory
Simple addressing modes with all load/store addresses being determined from register contents and instruction fields only
registers
ARM 11 has 31 general purpose 32-bit registers and 6 status registers
At any of times only 16 of these registers are visible and the others are used to speed up exception processing.
3 of those 16 visible registers have special roles (stack pointer, link register and program counter).
Instruction set
ARM 11 instruction set can be divided in 6 classes of instructions:
Branch instructions
Data processing instructions
Status register transfer instructions
Load and store instructions
Coprocessors instructions
Exception generating instructions