30-11-2012, 06:32 PM
An Efficient Implementation of Floating Point Multiplier
[attachment=42001]
INTRODUCTION
Floating point numbers are one possible way of
representing real numbers in binary format; the IEEE 754 [1]
standard presents two different floating point formats, Binary
interchange format and Decimal interchange format.
Multiplying floating point numbers is a critical requirement for
DSP applications involving large dynamic range. This paper
focuses only on single precision normalized binary interchange
format. Fig. 1 shows the IEEE 754 single precision binary
format representation; it consists of a one bit sign (S), an eight
bit exponent (E), and a twenty three bit fraction (M or
Mantissa). An extra bit is added to the fraction to form what is
called the significand1. If the exponent is greater than 0 and
smaller than 255, and there is 1 in the MSB of the significand
then the number is said to be a normalized number; in this case
the real number is represented by (1)
IMPLEMENTATION AND TESTING
The whole multiplier (top unit) was tested against the
Xilinx floating point multiplier core generated by Xilinx
coregen. Xilinx core was customized to have two flags to
indicate overflow and underflow, and to have a maximum
latency of three cycles. Xilinx core implements the “round to
nearest” rounding mode.
A testbench is used to generate the stimulus and applies it
to the implemented floating point multiplier and to the Xilinx
core then compares the results. The floating point multiplier
code was also checked using DesignChecker [7].
DesignChecker is a linting tool which helps in filtering design
issues like gated clocks, unused/undriven logic, and
combinational loops. The design was synthesized using
Precision synthesis tool [8] targeting Xilinx Virtex-5
5VFX200TFF1738 with a timing constraint of 300MHz. Post
synthesis and place and route simulations were made to ensure
the design functionality after synthesis and place and route.
Table IV shows the resources and frequency of the
implemented floating point multiplier and Xilinx core.
CONCLUSIONS AND FUTURE WORK
This paper presents an implementation of a floating point
multiplier that supports the IEEE 754-2008 binary interchange
format; the multiplier doesn’t implement rounding and just
presents the significand multiplication result as is (48 bits); this
gives better precision if the whole 48 bits are utilized in another
unit; i.e. a floating point adder to form a MAC unit. The design
has three pipelining stages and after implementation on a
Xilinx Virtex5 FPGA it achieves 301 MFLOPs.
[attachment=42001]
INTRODUCTION
Floating point numbers are one possible way of
representing real numbers in binary format; the IEEE 754 [1]
standard presents two different floating point formats, Binary
interchange format and Decimal interchange format.
Multiplying floating point numbers is a critical requirement for
DSP applications involving large dynamic range. This paper
focuses only on single precision normalized binary interchange
format. Fig. 1 shows the IEEE 754 single precision binary
format representation; it consists of a one bit sign (S), an eight
bit exponent (E), and a twenty three bit fraction (M or
Mantissa). An extra bit is added to the fraction to form what is
called the significand1. If the exponent is greater than 0 and
smaller than 255, and there is 1 in the MSB of the significand
then the number is said to be a normalized number; in this case
the real number is represented by (1)
IMPLEMENTATION AND TESTING
The whole multiplier (top unit) was tested against the
Xilinx floating point multiplier core generated by Xilinx
coregen. Xilinx core was customized to have two flags to
indicate overflow and underflow, and to have a maximum
latency of three cycles. Xilinx core implements the “round to
nearest” rounding mode.
A testbench is used to generate the stimulus and applies it
to the implemented floating point multiplier and to the Xilinx
core then compares the results. The floating point multiplier
code was also checked using DesignChecker [7].
DesignChecker is a linting tool which helps in filtering design
issues like gated clocks, unused/undriven logic, and
combinational loops. The design was synthesized using
Precision synthesis tool [8] targeting Xilinx Virtex-5
5VFX200TFF1738 with a timing constraint of 300MHz. Post
synthesis and place and route simulations were made to ensure
the design functionality after synthesis and place and route.
Table IV shows the resources and frequency of the
implemented floating point multiplier and Xilinx core.
CONCLUSIONS AND FUTURE WORK
This paper presents an implementation of a floating point
multiplier that supports the IEEE 754-2008 binary interchange
format; the multiplier doesn’t implement rounding and just
presents the significand multiplication result as is (48 bits); this
gives better precision if the whole 48 bits are utilized in another
unit; i.e. a floating point adder to form a MAC unit. The design
has three pipelining stages and after implementation on a
Xilinx Virtex5 FPGA it achieves 301 MFLOPs.