06-12-2012, 11:59 AM
IMPLEMENTATION OF A 6.5MHZ 34-8 NCO
[attachment=42748]
lNTRODUCTlON
Compared to the traditional voltage controlled oscillator (CO), the numerically
controlled oscillator has advantages of wide frequency tuning range, short frequency
tuning time, fine frequency resolution and controlled by digital word instead of voltage
that make it accurate and convenient for digital communication system.
In 1971, J. Tierney first proposed the direct digital frequency synthesis schemes. The
original design model was put forward by Hamil W. Cooper in 1974. The oscillator, under
numeric control, generates output frequencies based on the equation below:
fo = K (fd2N)
where
fo output frequency of the NCO
fc accumulator clock frequency
N number of bits in the accumulator
K frequency control number
The output frequency step is fc/2N. The maximum sine output frequency can approach tG
fc/2 with ideal filter.
After that, NCO was gradually coming into VLSl technology and the primary focus
of recent work in this field has been to improve clock frequency, extend function, simplify
the structure, etc. The memory scheme to reduce the. size of ROM (phase-to-amplitude
converter), and the structure of pipelined accumulator or progression-of-state technique to
improve the speed of accumulator was proposed in succession.
To reduce the running time, a pipelined structure NCO is described in this paper.
The design adopt ROM to memory the phase-amplitude covert relationship of sine wave.
Considering the symmetry with the 0 and 18Gdegree axis and also the 90 and 270-degree
axis, the memory volume can be decreased by a factor of four. A sense amplifier is used
TO reduce the reading time. The function of phase controlling is added to determine the
jhase return to zero or maintain continuity when output frequency altered, and 9-bit sine
'wave output and 10-bit phase output is provided. The maximum output frequency is
iimited at fc/4 to eliminate the difficulty of filter.
Phase-AmDlitude Converter -- ROM
The sine phaseamplitude conversion is completed by looking up ROM. Since the
symmetry of sine wave, only the h i 2 phase-amplitude relationship is needed. The l0-bit
phase codes are devided into 2-bit quadrant codes and 8-bit phase deviation codes
accordingly. The 8-bit phase deviation codes act as ROM address codes directly in I, 111
quadrant and completion of the 8-bit phase deviation codes act as ROM address codes in
II, N quadrant, controlled by 2-bit quadrant codes. The sign of amplitude is decided by the
quadrant codes also, positive in I, II quadrant and negative in 111, IV quadrant.
Testina- Circuit
The major parts of NCO are accumulator and ROM. In order to analysis any desired
part of circuit in function, performance. fault and other aspects, it is desired that the two
part can be tested separately, Considering of NCO have a lot of registers, the addition of
some multiplexers can achieve the controllability and observability of inner point. This way
simplify the generation of testing code as well as the test carry out without large cost of
hardware.
After logic design and test design, employ BBL design method based on standard
cell and auto-placing and routing tool to complete the layout design &er finishing logic
and test design to guarantee the rightness, adopt post simulation to ensure the first time
success. The drive captivity is also considered to meet the demands of users.
FABRICATION AND TEST RESULTS
The NCO chip has been fabricated through standard 2um P-well CMOS technology
with single layer polysilicon. single layer metal. The total number of transistors is about 9ooo.
The 28-pad chip size is 3.4*3.5mm2.
The test is carried out on IMS(1ntegrated Measurement System) XL-40. When input
high voltage set at 3.N. input low voltage set at 230mV and switching voltage set at 1.9V.
the test result of NCO half clock period achieves 77nS by means of frequency scanning,
the NCO frequency is 6.5 MHz accordingly. The test result of output current capacity is
more than 5.9mA when high voltage is more than 4.48V and low is voltage le
and the input leakage current is less than 503pA when high voltage is 5V and
is ov.
CONCLUTIONS
An numerically controlled oscillator chip, using pipelined structure, has been
developed in standard 2um P well CMOS technology. The typical maximum input clock
rate is 6.5MHZ.
By analysis, the factors limiting speed improved are the delay of accumulator and
the data acquiring rate of ROM. Through the use of improving pipelined structure and Nwell
CMOS technology, an NCO device with clock rate in excess of lOMHZ is in deed
possible.
[attachment=42748]
lNTRODUCTlON
Compared to the traditional voltage controlled oscillator (CO), the numerically
controlled oscillator has advantages of wide frequency tuning range, short frequency
tuning time, fine frequency resolution and controlled by digital word instead of voltage
that make it accurate and convenient for digital communication system.
In 1971, J. Tierney first proposed the direct digital frequency synthesis schemes. The
original design model was put forward by Hamil W. Cooper in 1974. The oscillator, under
numeric control, generates output frequencies based on the equation below:
fo = K (fd2N)
where
fo output frequency of the NCO
fc accumulator clock frequency
N number of bits in the accumulator
K frequency control number
The output frequency step is fc/2N. The maximum sine output frequency can approach tG
fc/2 with ideal filter.
After that, NCO was gradually coming into VLSl technology and the primary focus
of recent work in this field has been to improve clock frequency, extend function, simplify
the structure, etc. The memory scheme to reduce the. size of ROM (phase-to-amplitude
converter), and the structure of pipelined accumulator or progression-of-state technique to
improve the speed of accumulator was proposed in succession.
To reduce the running time, a pipelined structure NCO is described in this paper.
The design adopt ROM to memory the phase-amplitude covert relationship of sine wave.
Considering the symmetry with the 0 and 18Gdegree axis and also the 90 and 270-degree
axis, the memory volume can be decreased by a factor of four. A sense amplifier is used
TO reduce the reading time. The function of phase controlling is added to determine the
jhase return to zero or maintain continuity when output frequency altered, and 9-bit sine
'wave output and 10-bit phase output is provided. The maximum output frequency is
iimited at fc/4 to eliminate the difficulty of filter.
Phase-AmDlitude Converter -- ROM
The sine phaseamplitude conversion is completed by looking up ROM. Since the
symmetry of sine wave, only the h i 2 phase-amplitude relationship is needed. The l0-bit
phase codes are devided into 2-bit quadrant codes and 8-bit phase deviation codes
accordingly. The 8-bit phase deviation codes act as ROM address codes directly in I, 111
quadrant and completion of the 8-bit phase deviation codes act as ROM address codes in
II, N quadrant, controlled by 2-bit quadrant codes. The sign of amplitude is decided by the
quadrant codes also, positive in I, II quadrant and negative in 111, IV quadrant.
Testina- Circuit
The major parts of NCO are accumulator and ROM. In order to analysis any desired
part of circuit in function, performance. fault and other aspects, it is desired that the two
part can be tested separately, Considering of NCO have a lot of registers, the addition of
some multiplexers can achieve the controllability and observability of inner point. This way
simplify the generation of testing code as well as the test carry out without large cost of
hardware.
After logic design and test design, employ BBL design method based on standard
cell and auto-placing and routing tool to complete the layout design &er finishing logic
and test design to guarantee the rightness, adopt post simulation to ensure the first time
success. The drive captivity is also considered to meet the demands of users.
FABRICATION AND TEST RESULTS
The NCO chip has been fabricated through standard 2um P-well CMOS technology
with single layer polysilicon. single layer metal. The total number of transistors is about 9ooo.
The 28-pad chip size is 3.4*3.5mm2.
The test is carried out on IMS(1ntegrated Measurement System) XL-40. When input
high voltage set at 3.N. input low voltage set at 230mV and switching voltage set at 1.9V.
the test result of NCO half clock period achieves 77nS by means of frequency scanning,
the NCO frequency is 6.5 MHz accordingly. The test result of output current capacity is
more than 5.9mA when high voltage is more than 4.48V and low is voltage le
and the input leakage current is less than 503pA when high voltage is 5V and
is ov.
CONCLUTIONS
An numerically controlled oscillator chip, using pipelined structure, has been
developed in standard 2um P well CMOS technology. The typical maximum input clock
rate is 6.5MHZ.
By analysis, the factors limiting speed improved are the delay of accumulator and
the data acquiring rate of ROM. Through the use of improving pipelined structure and Nwell
CMOS technology, an NCO device with clock rate in excess of lOMHZ is in deed
possible.