06-12-2012, 04:29 PM
The Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET)
[attachment=42818]
INTRODUCTION TO MOSFET
The Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals ,the body (or substrate) of the MOSFET often is connected to the source terminal, making it a three-terminal device like other field-effect transistors.
In enhancement mode MOSFETs, a voltage drop across the oxide induces a conducting channel between the source and drain contacts via the field effect. The term "enhancement mode" refers to the increase of conductivity with increase in oxide field that adds carriers to the channel, also referred to as the inversion layer
The n-type Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) consists of a source and a drain, two highly conducting n-type semiconductor regions which are isolated from the p-type substrate by reversed-biased p-n diodes.
SOI Technology
The traditional integrated circuit technoloy is associated with the concept of integrated circuit conceived by Noyce and Kilby, where multiple transistors could be made in the same piece of Si by insolating neighbouring devices from each other with reverse biased p-n junctions, field oxides or stop channels.
The solution of these problems demand a total reconsideration of the classical concepts that have been used in all designs aspects till now. Therefore, it is neccesary to optimize all the areas involved in the production, from the substrate manufacture, device improvement, new architectures for microprocessors and finishing with the redefination of the encapsulation and external interconnections.
The new innovative concept must be compatible with the present processors and techniques to ensure a gradual reconversion of the current technology and recovering in that way, the huge amount of money invested in clean rooms.
SOI Technology Motivations
It is possible and in some ases advantageous, to build monolithic semiconductor circuits with dielectrics, instead of junction, isolation. This is accomplished by utilizing silicon-on-insulator (SOI) WAFERS. Since one decade, commercial applications of SOI have grown exponentially, and entered the mainstream of ultralarge (ULSI) electronic circuits.
In second place, currently, performance enhancement motivates many integrated circuits companies to use SOI wafers. For the same supply voltage, digital logic circuits, such as microprocessors, run faster in SOIthan in bulk Si. Alternatively, it is possible to reduce power consumptions of SOI chips by lowering thir operating voltage, while still keeping the clock rate,I.e. their performance which is the same in more power wasteful circuits.
The change from the technology hasn’t been so critical as it was thought in the beginning. Once the technological challenge of makink crystal silicon films on a dielectric substrate has been overcome, the circuit design is similar to the one used on the previous technology. In practice, it is not neccesary to introduce heavy modifications in the design to translate a conventional bulk circuit into SOI.
Advantages Of SOI Technology
Most of the technological processes related to the SOI devices manufacture are compatible with the standards of the semiconductor industry, the final cost of the product is slightly higher than the conventional technology essentially due to the pre-processing of the wafers for each application. Among the main advantages should be mentioned:
1. Reduction of parasitic capacitance and junction depth.
2. Full compatible technology with the traditional process.
3. Steps reduction in the manufacture process.
4. In some cases, increase of the level of integration due to the layout simplification.
5. Ionizing radiation hardness devices.
SOI MOSFET
In electronics, a SOI MOSFET semiconductor device is a silicon on insulator (SOI) MOSFET structure in which a semiconductor layer, e.g. silicon, germanium or the like, is formed above an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate SOI MOSFET devices are adapted for use by the computer industry. The buried oxide layer can be used in SRAM memory designs. There are two type of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For n-type PDSOI MOSFET the sandwiched p-type film between the gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region can't cover the whole p region. So to some extent PDSOI behaves like bulk MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole film. In FDSOI the front gate (GOX) supports less depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. Other drawbacks in bulk MOSFETs, like threshold voltage roll off, higher sub-threshold slop body effect, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "floating body effect (FBE)" since the film is not connected to any of the supplies.
Partially Depleted MOSFETs
In partially depleted (PD) SOI MOSFETs, the depletion region induced by the gates does not extend from one interface to another and a neutral region subsists between the two insulators .The interface coupling effects are not present , but instead floating-body effects arise ,including kink effect, transient variations of the potential, threshold voltage and current.
Fully Depleted MOSFETs
Full depletion happens when the depletion region covers the whole transistor body .The depletion charge is constant and cannot extend further when the gate bias increases .The excellent coupling between the gate and the inversion charge offers improved current and subthreshold slope. The front and back surface potentials become inter-related. Interface coupling means that the electrical characteristics of one channel vary with the opposite gate bias. In practice front- gate measurement may include contributions from the BOX and from the BOX/bulk interface, and highly depends on the back-gate bias.FD characteristics are complex, controlled by both gate voltages.
Simulation Tool and its Need
As the complexity and challenges in semiconductor technology increases, there is a great need for some powerful simulation tools to aid in design and solution of the problems. Design, fabrication and characterization on transistors are getting much more complex with methods of solving short channel effects and scaling MOSFET’s channel has become much more complicated.
Although the main material used to fabricate MOSFET is just silicon, which considered a low cost material, the failure fabrication in the trial and error process might also create unwanted wastes and cause the pollutions to the environment. As such, the simulation tool becomes necessary today, as it allows virtual fabrication, simulate and emulate the characteristics of the fabricated devices. With it, engineers, researcher and analysts can make better improvement to the MOSFET design.
Simulation of Fully depleted SOI MOSFET
The continuing trend for high speed circuits has resulted in marked increase in application of silicon-on-insulator MOSFET (SOI MOSFET). However SOI MOSFET offers a much more difficult in simulation problem due to presence of significant floating body effects, carrier heating and non-localized transport phenomenon. I have simulated a single gate SOI MOSFETS by using a code (Appendix A) with the latest release of Silvaco’s 2D semiconductor device simulator ATLAS now accounts for all non-localized and lattice heating effects.
[attachment=42818]
INTRODUCTION TO MOSFET
The Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals ,the body (or substrate) of the MOSFET often is connected to the source terminal, making it a three-terminal device like other field-effect transistors.
In enhancement mode MOSFETs, a voltage drop across the oxide induces a conducting channel between the source and drain contacts via the field effect. The term "enhancement mode" refers to the increase of conductivity with increase in oxide field that adds carriers to the channel, also referred to as the inversion layer
The n-type Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) consists of a source and a drain, two highly conducting n-type semiconductor regions which are isolated from the p-type substrate by reversed-biased p-n diodes.
SOI Technology
The traditional integrated circuit technoloy is associated with the concept of integrated circuit conceived by Noyce and Kilby, where multiple transistors could be made in the same piece of Si by insolating neighbouring devices from each other with reverse biased p-n junctions, field oxides or stop channels.
The solution of these problems demand a total reconsideration of the classical concepts that have been used in all designs aspects till now. Therefore, it is neccesary to optimize all the areas involved in the production, from the substrate manufacture, device improvement, new architectures for microprocessors and finishing with the redefination of the encapsulation and external interconnections.
The new innovative concept must be compatible with the present processors and techniques to ensure a gradual reconversion of the current technology and recovering in that way, the huge amount of money invested in clean rooms.
SOI Technology Motivations
It is possible and in some ases advantageous, to build monolithic semiconductor circuits with dielectrics, instead of junction, isolation. This is accomplished by utilizing silicon-on-insulator (SOI) WAFERS. Since one decade, commercial applications of SOI have grown exponentially, and entered the mainstream of ultralarge (ULSI) electronic circuits.
In second place, currently, performance enhancement motivates many integrated circuits companies to use SOI wafers. For the same supply voltage, digital logic circuits, such as microprocessors, run faster in SOIthan in bulk Si. Alternatively, it is possible to reduce power consumptions of SOI chips by lowering thir operating voltage, while still keeping the clock rate,I.e. their performance which is the same in more power wasteful circuits.
The change from the technology hasn’t been so critical as it was thought in the beginning. Once the technological challenge of makink crystal silicon films on a dielectric substrate has been overcome, the circuit design is similar to the one used on the previous technology. In practice, it is not neccesary to introduce heavy modifications in the design to translate a conventional bulk circuit into SOI.
Advantages Of SOI Technology
Most of the technological processes related to the SOI devices manufacture are compatible with the standards of the semiconductor industry, the final cost of the product is slightly higher than the conventional technology essentially due to the pre-processing of the wafers for each application. Among the main advantages should be mentioned:
1. Reduction of parasitic capacitance and junction depth.
2. Full compatible technology with the traditional process.
3. Steps reduction in the manufacture process.
4. In some cases, increase of the level of integration due to the layout simplification.
5. Ionizing radiation hardness devices.
SOI MOSFET
In electronics, a SOI MOSFET semiconductor device is a silicon on insulator (SOI) MOSFET structure in which a semiconductor layer, e.g. silicon, germanium or the like, is formed above an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate SOI MOSFET devices are adapted for use by the computer industry. The buried oxide layer can be used in SRAM memory designs. There are two type of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For n-type PDSOI MOSFET the sandwiched p-type film between the gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region can't cover the whole p region. So to some extent PDSOI behaves like bulk MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole film. In FDSOI the front gate (GOX) supports less depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. Other drawbacks in bulk MOSFETs, like threshold voltage roll off, higher sub-threshold slop body effect, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "floating body effect (FBE)" since the film is not connected to any of the supplies.
Partially Depleted MOSFETs
In partially depleted (PD) SOI MOSFETs, the depletion region induced by the gates does not extend from one interface to another and a neutral region subsists between the two insulators .The interface coupling effects are not present , but instead floating-body effects arise ,including kink effect, transient variations of the potential, threshold voltage and current.
Fully Depleted MOSFETs
Full depletion happens when the depletion region covers the whole transistor body .The depletion charge is constant and cannot extend further when the gate bias increases .The excellent coupling between the gate and the inversion charge offers improved current and subthreshold slope. The front and back surface potentials become inter-related. Interface coupling means that the electrical characteristics of one channel vary with the opposite gate bias. In practice front- gate measurement may include contributions from the BOX and from the BOX/bulk interface, and highly depends on the back-gate bias.FD characteristics are complex, controlled by both gate voltages.
Simulation Tool and its Need
As the complexity and challenges in semiconductor technology increases, there is a great need for some powerful simulation tools to aid in design and solution of the problems. Design, fabrication and characterization on transistors are getting much more complex with methods of solving short channel effects and scaling MOSFET’s channel has become much more complicated.
Although the main material used to fabricate MOSFET is just silicon, which considered a low cost material, the failure fabrication in the trial and error process might also create unwanted wastes and cause the pollutions to the environment. As such, the simulation tool becomes necessary today, as it allows virtual fabrication, simulate and emulate the characteristics of the fabricated devices. With it, engineers, researcher and analysts can make better improvement to the MOSFET design.
Simulation of Fully depleted SOI MOSFET
The continuing trend for high speed circuits has resulted in marked increase in application of silicon-on-insulator MOSFET (SOI MOSFET). However SOI MOSFET offers a much more difficult in simulation problem due to presence of significant floating body effects, carrier heating and non-localized transport phenomenon. I have simulated a single gate SOI MOSFETS by using a code (Appendix A) with the latest release of Silvaco’s 2D semiconductor device simulator ATLAS now accounts for all non-localized and lattice heating effects.