25-08-2017, 09:32 PM
Introduction to 8086 Microprocessor
[attachment=43707]
Intel 8086 Microprocessor
Key Features:
Released by Intel in 1978
Produced from 1978 to 1990s
A 16-bit microprocessor chip.
Max. CPU clock rate :
5 MHz to 10 MHz
Instruction set: x86-16
Package: 40 pin DIP
The 8086 gave rise to the x86 architecture of Intel's future processors.
Architecture of 8086
The architecture of 8086 includes
Arithmetic Logic Unit (ALU)
Flags
General registers
Instruction byte queue
Segment registers
EU & BIU
The 8086 CPU logic has been partitioned into two functional units namely Bus Interface Unit (BIU) and Execution Unit (EU)
The major reason for this separation is to increase the processing speed of the processor
The BIU has to interact with memory and input and output devices in fetching the instructions and data required by the EU
EU is responsible for executing the instructions of the programs and to carry out the required processing
Execution Unit
The Execution Unit (EU) has
Control unit
Instruction decoder
Arithmetic and Logical Unit (ALU)
General registers
Flag register
Pointers
Index registers
Control unit is responsible for the co-ordination of all other units of the processor
ALU performs various arithmetic and logical operations over the data
The instruction decoder translates the instructions fetched from the memory into a series of actions that are carried out by the EU
Execution Unit - Registers
General registers are used for temporary storage and manipulation of data and instructions
Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX
Accumulator can be used for I/O operations and string manipulation
Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX
BX register usually contains a data pointer used for based, based indexed or register indirect addressing
Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX
Count register can be used as a counter in string manipulation and shift/rotate instructions
Execution Unit - Flags
Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts
Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction
Execution Unit - Pointers
Stack Pointer (SP) is a 16-bit register pointing to program stack
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data addresses in string manipulation instructions
BIU – Instruction Byte Queue
Execution and decoding of certain instructions do not require the use of buses
While such instructions are executed, the BIU fetches up to six instruction bytes for the following instructions (the subsequent instructions)
The BIU store these prefetched bytes in a first-in-first out register by name instruction byte queue
When the EU is ready for its next instruction, it simply reads the instruction byte(s) for the instruction from the queue in BIU
Segment: Offset Notation
The total addressable memory size is 1MB
Most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory
To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory
A simple scheme would be to order the bytes in a serial fashion and number them from 0 (or 1) to the end of memory
The scheme used in the 8086 is called segmentation
Every address has two parts, a SEGMENT and an OFFSET (Segmnet:Offset )
The segment indicates the starting of a 64 kilobyte portion of memory, in multiples of 16
The offset indicates the position within the 64k portion
Absolute address = (segment * 16) + offset
Segment Registers
The memory of 8086 is divided into 4 segments namely
Code segment (program memory)
Data segment (data memory)
Stack segment (stack memory )
Extra segment (extra memory)
Different Areas in Memory
Program memory – Program can be located anywhere in memory
Data memory – The processor can access data in any one out of 4 available segments
Stack memory – A stack is a section of the memory set aside to store addresses and data while a subprogram executes
Extra segment – This segment is also similar to data memory where additional data may be stored and maintained
[attachment=43707]
Intel 8086 Microprocessor
Key Features:
Released by Intel in 1978
Produced from 1978 to 1990s
A 16-bit microprocessor chip.
Max. CPU clock rate :
5 MHz to 10 MHz
Instruction set: x86-16
Package: 40 pin DIP
The 8086 gave rise to the x86 architecture of Intel's future processors.
Architecture of 8086
The architecture of 8086 includes
Arithmetic Logic Unit (ALU)
Flags
General registers
Instruction byte queue
Segment registers
EU & BIU
The 8086 CPU logic has been partitioned into two functional units namely Bus Interface Unit (BIU) and Execution Unit (EU)
The major reason for this separation is to increase the processing speed of the processor
The BIU has to interact with memory and input and output devices in fetching the instructions and data required by the EU
EU is responsible for executing the instructions of the programs and to carry out the required processing
Execution Unit
The Execution Unit (EU) has
Control unit
Instruction decoder
Arithmetic and Logical Unit (ALU)
General registers
Flag register
Pointers
Index registers
Control unit is responsible for the co-ordination of all other units of the processor
ALU performs various arithmetic and logical operations over the data
The instruction decoder translates the instructions fetched from the memory into a series of actions that are carried out by the EU
Execution Unit - Registers
General registers are used for temporary storage and manipulation of data and instructions
Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX
Accumulator can be used for I/O operations and string manipulation
Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX
BX register usually contains a data pointer used for based, based indexed or register indirect addressing
Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX
Count register can be used as a counter in string manipulation and shift/rotate instructions
Execution Unit - Flags
Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts
Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction
Execution Unit - Pointers
Stack Pointer (SP) is a 16-bit register pointing to program stack
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data addresses in string manipulation instructions
BIU – Instruction Byte Queue
Execution and decoding of certain instructions do not require the use of buses
While such instructions are executed, the BIU fetches up to six instruction bytes for the following instructions (the subsequent instructions)
The BIU store these prefetched bytes in a first-in-first out register by name instruction byte queue
When the EU is ready for its next instruction, it simply reads the instruction byte(s) for the instruction from the queue in BIU
Segment: Offset Notation
The total addressable memory size is 1MB
Most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory
To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory
A simple scheme would be to order the bytes in a serial fashion and number them from 0 (or 1) to the end of memory
The scheme used in the 8086 is called segmentation
Every address has two parts, a SEGMENT and an OFFSET (Segmnet:Offset )
The segment indicates the starting of a 64 kilobyte portion of memory, in multiples of 16
The offset indicates the position within the 64k portion
Absolute address = (segment * 16) + offset
Segment Registers
The memory of 8086 is divided into 4 segments namely
Code segment (program memory)
Data segment (data memory)
Stack segment (stack memory )
Extra segment (extra memory)
Different Areas in Memory
Program memory – Program can be located anywhere in memory
Data memory – The processor can access data in any one out of 4 available segments
Stack memory – A stack is a section of the memory set aside to store addresses and data while a subprogram executes
Extra segment – This segment is also similar to data memory where additional data may be stored and maintained