20-12-2012, 03:21 PM
Evolution of DSPs
[attachment=44583]
Abstract
DSP algorithms and necessity to do complex computation with strict time and accuracy constraints
pioneered to the development in the architecture of digital signal processors. Different low and high
end DSPs, which satisfies cost and speed constrains of various application are available in the market.
This report reviews the available DSP processor architecture and their features. There is growing need
to design customized DSP core, which suits to particular application. This fact is explained with the
case study of DSP architecture designed for handheld devices such as mobile phones.
Introduction:
DSP has become a key component in many consumer, communication, medical, and industrial
products. The number and variety of products that include some form of digital signal processing has
grown dramatically over the years. These products use a variety of hardware approaches to implement
DSP, ranging from the use of microprocessors to field-programmable gate arrays (FPGAs) to custom
integrated circuits (ICs).
In comparison to microprocessors, DSP processors often have an advantage in terms of speed, cost,
and energy efficiency. In this report, we trace the evolution of DSP processors, from early
architectures to current state-of-the-art devices. Some of the key differences among architectures, and
their strengths and weaknesses are highlighted. Lastly, the case study of SPXK5, used in handheld
applications is presented to explain how customized hardware are being used to satisfy need of
particular application.
Differences in DSP and General-Purpose Processors Architecture:
From the beginning, DSP algorithms have driven DSP processor architectures. For nearly every
feature found in a DSP processor, there are associated DSP algorithms whose computation, in some
way are eased by inclusion of the feature. Therefore, perhaps the best way to understand the evolution
of DSP architectures is to look at typical DSP algorithms and identify how their computational
requirements have influenced the architectures of DSP processors [1]. As a case study, we will
consider one of the most common signal processing algorithms, the FIR filter.
Fast Multipliers
The FIR filter is mathematically expressed as, where is a vector of input data, and is a vector of filter
coefficients. For each “tap” of the filter, a data sample is multiplied by a filter coefficient, with the
result added to a running sum for all of the taps. Hence, the main component of the FIR filter
algorithm is “multiply and add”. These operations are not unique to the FIR filter algorithm, in fact,
multiplication (often combined with accumulation of products) is one of the most common operations
performed in signal processing convolution, IIR filtering, and Fourier transforms also all involve
heavy use of multiply accumulate operations.
Originally, microprocessors implemented multiplications by a series of shift and add operations, each
of which consumed one or more clock cycles. In 1982, however, Texas Instruments (TI) introduced
the first commercially successful “DSP processor,” the TMS32010, which incorporated specialized
hardware to enable it to compute a multiplication in a single clock cycle. As might be expected, faster
multiplication hardware yields faster performance in many DSP algorithms, and for this reason all
DSP processors include at least one dedicated single cycle multiplier or combined multiplyaccumulate
(MAC) unit.
Multiple Execution Units
DSP applications typically have very high computational requirements in comparison to other types of
computing tasks, since they often must execute DSP algorithms (such as FIR filtering) in real time on
lengthy segments of signals sampled at 10-100 KHz or higher. Hence, DSP processors often include
several independent execution units that are capable of operating in parallel. For example, in addition
to the MAC unit; they typically contain an arithmetic-logic unit (ALU) and a shifter.
Efficient Memory Accesses
Executing a MAC in every clock cycle requires more than just a single-cycle MAC unit. It also
requires the ability to fetch the MAC instruction, a data sample, and a filter coefficient from memory
in a single cycle. Hence, good DSP performance requires high memory bandwidth higher than was
supported on the general-purpose microprocessors, which typically contained a single bus connection
to memory and could only make one access per clock cycle. To address the need for increased
memory bandwidth, early DSP processors developed different memory architectures that could
support multiple memory accesses per cycle. The most common approach (still commonly used) was
to use two or more separate banks of memory, each of which was accessed by its own bus and could
be read or written during every clock cycle. Often, instructions were stored in one memory bank,
while data was stored in another. With this arrangement, the processor could fetch an instruction and a
data operand in parallel in every cycle.
Data Format
Most DSP processors use a fixed-point numeric data type instead of the floating-point format. Though
floating-point format have good numerical fidelity and virtually eliminates, numerical overflow etc, in
many cases DSP processors face additional constraints i.e. they must be inexpensive and provide good
energy efficiency. Fixed-point processors tend to be cheaper and less power-hungry than floatingpoint
processors at comparable speeds, because floating-point formats require more complex
hardware to implement. To ensure adequate signal quality while using fixed-point data, DSP
processors typically include specialized hardware to help programmers maintain numeric fidelity
throughout a series of computations. For example, most DSP processors include one or more
“ accumulator” registers to hold the results of summing several multiplication products. Accumulator
registers are typically wider than other registers; they often provide extra bits, called “ guard bits,” to
extend the range of values that can be represented and thus avoid overflow.
Multi-Issue Architectures
Enhanced-conventional DSP processors provide improved performance by allowing more operations
to be encoded in every instruction, however they are difficult to program in the assembly language
and are unfriendly compiler targets.
With the goals of achieving high performance and creating architecture that lends itself to the use of
compilers, DSP processors with multi-issue approach were designed. In contrast to conventional and
enhanced-conventional processors, multi-issue processors use very simple instructions that typically
encode a single operation. These processors achieve a high level of parallelism by issuing and
executing instructions in parallel groups rather than one at a time. Using simple instructions simplifies
instruction decoding and execution, allowing multi-issue processors to execute at higher clock rates
than conventional or enhanced conventional DSP processors.
Conclusions
DSP processor architectures are evolving to meet the changing needs of DSP applications. There are
many diverse architecture are designed to address different issues and goals. The forces driving the
evolution of DSP processors today include the persistent push for increased speed, decreased energy
consumption, decreased memory usage, and decreased cost, to better meet the needs of new and
existing applications. As shown with example of DSP processors for low power Mobile application
customized products are coming up to address the new generation applications.
The emphasis is for architectures that facilitate development of more efficient compilers, allowing
DSP applications to be written primarily in high-level languages. This has become a focal point in the
design of new DSP processors, because DSP applications are growing too large to comfortably
implement and maintain in assembly language. As the needs of DSP applications continue to change,
we expect to see a continuing evolution in DSP processors.
[attachment=44583]
Abstract
DSP algorithms and necessity to do complex computation with strict time and accuracy constraints
pioneered to the development in the architecture of digital signal processors. Different low and high
end DSPs, which satisfies cost and speed constrains of various application are available in the market.
This report reviews the available DSP processor architecture and their features. There is growing need
to design customized DSP core, which suits to particular application. This fact is explained with the
case study of DSP architecture designed for handheld devices such as mobile phones.
Introduction:
DSP has become a key component in many consumer, communication, medical, and industrial
products. The number and variety of products that include some form of digital signal processing has
grown dramatically over the years. These products use a variety of hardware approaches to implement
DSP, ranging from the use of microprocessors to field-programmable gate arrays (FPGAs) to custom
integrated circuits (ICs).
In comparison to microprocessors, DSP processors often have an advantage in terms of speed, cost,
and energy efficiency. In this report, we trace the evolution of DSP processors, from early
architectures to current state-of-the-art devices. Some of the key differences among architectures, and
their strengths and weaknesses are highlighted. Lastly, the case study of SPXK5, used in handheld
applications is presented to explain how customized hardware are being used to satisfy need of
particular application.
Differences in DSP and General-Purpose Processors Architecture:
From the beginning, DSP algorithms have driven DSP processor architectures. For nearly every
feature found in a DSP processor, there are associated DSP algorithms whose computation, in some
way are eased by inclusion of the feature. Therefore, perhaps the best way to understand the evolution
of DSP architectures is to look at typical DSP algorithms and identify how their computational
requirements have influenced the architectures of DSP processors [1]. As a case study, we will
consider one of the most common signal processing algorithms, the FIR filter.
Fast Multipliers
The FIR filter is mathematically expressed as, where is a vector of input data, and is a vector of filter
coefficients. For each “tap” of the filter, a data sample is multiplied by a filter coefficient, with the
result added to a running sum for all of the taps. Hence, the main component of the FIR filter
algorithm is “multiply and add”. These operations are not unique to the FIR filter algorithm, in fact,
multiplication (often combined with accumulation of products) is one of the most common operations
performed in signal processing convolution, IIR filtering, and Fourier transforms also all involve
heavy use of multiply accumulate operations.
Originally, microprocessors implemented multiplications by a series of shift and add operations, each
of which consumed one or more clock cycles. In 1982, however, Texas Instruments (TI) introduced
the first commercially successful “DSP processor,” the TMS32010, which incorporated specialized
hardware to enable it to compute a multiplication in a single clock cycle. As might be expected, faster
multiplication hardware yields faster performance in many DSP algorithms, and for this reason all
DSP processors include at least one dedicated single cycle multiplier or combined multiplyaccumulate
(MAC) unit.
Multiple Execution Units
DSP applications typically have very high computational requirements in comparison to other types of
computing tasks, since they often must execute DSP algorithms (such as FIR filtering) in real time on
lengthy segments of signals sampled at 10-100 KHz or higher. Hence, DSP processors often include
several independent execution units that are capable of operating in parallel. For example, in addition
to the MAC unit; they typically contain an arithmetic-logic unit (ALU) and a shifter.
Efficient Memory Accesses
Executing a MAC in every clock cycle requires more than just a single-cycle MAC unit. It also
requires the ability to fetch the MAC instruction, a data sample, and a filter coefficient from memory
in a single cycle. Hence, good DSP performance requires high memory bandwidth higher than was
supported on the general-purpose microprocessors, which typically contained a single bus connection
to memory and could only make one access per clock cycle. To address the need for increased
memory bandwidth, early DSP processors developed different memory architectures that could
support multiple memory accesses per cycle. The most common approach (still commonly used) was
to use two or more separate banks of memory, each of which was accessed by its own bus and could
be read or written during every clock cycle. Often, instructions were stored in one memory bank,
while data was stored in another. With this arrangement, the processor could fetch an instruction and a
data operand in parallel in every cycle.
Data Format
Most DSP processors use a fixed-point numeric data type instead of the floating-point format. Though
floating-point format have good numerical fidelity and virtually eliminates, numerical overflow etc, in
many cases DSP processors face additional constraints i.e. they must be inexpensive and provide good
energy efficiency. Fixed-point processors tend to be cheaper and less power-hungry than floatingpoint
processors at comparable speeds, because floating-point formats require more complex
hardware to implement. To ensure adequate signal quality while using fixed-point data, DSP
processors typically include specialized hardware to help programmers maintain numeric fidelity
throughout a series of computations. For example, most DSP processors include one or more
“ accumulator” registers to hold the results of summing several multiplication products. Accumulator
registers are typically wider than other registers; they often provide extra bits, called “ guard bits,” to
extend the range of values that can be represented and thus avoid overflow.
Multi-Issue Architectures
Enhanced-conventional DSP processors provide improved performance by allowing more operations
to be encoded in every instruction, however they are difficult to program in the assembly language
and are unfriendly compiler targets.
With the goals of achieving high performance and creating architecture that lends itself to the use of
compilers, DSP processors with multi-issue approach were designed. In contrast to conventional and
enhanced-conventional processors, multi-issue processors use very simple instructions that typically
encode a single operation. These processors achieve a high level of parallelism by issuing and
executing instructions in parallel groups rather than one at a time. Using simple instructions simplifies
instruction decoding and execution, allowing multi-issue processors to execute at higher clock rates
than conventional or enhanced conventional DSP processors.
Conclusions
DSP processor architectures are evolving to meet the changing needs of DSP applications. There are
many diverse architecture are designed to address different issues and goals. The forces driving the
evolution of DSP processors today include the persistent push for increased speed, decreased energy
consumption, decreased memory usage, and decreased cost, to better meet the needs of new and
existing applications. As shown with example of DSP processors for low power Mobile application
customized products are coming up to address the new generation applications.
The emphasis is for architectures that facilitate development of more efficient compilers, allowing
DSP applications to be written primarily in high-level languages. This has become a focal point in the
design of new DSP processors, because DSP applications are growing too large to comfortably
implement and maintain in assembly language. As the needs of DSP applications continue to change,
we expect to see a continuing evolution in DSP processors.