20-12-2012, 06:52 PM
64-megabit 2.7-volt Dual-interface DataFlash
[attachment=44665]
Description
The AT45DB642D is a 2.7-volt, dual-interface sequential access Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications. The
AT45DB642D supports RapidS serial interface and Rapid8 8-bit interface. RapidS serial interface
is SPI compatible for frequencies up to 66 MHz. The dual-interface allows a dedicated
serial interface to be connected to a DSP and a dedicated 8-bit interface to be connected to a
microcontroller or vice versa. However, the use of either interface is purely optional. Its
69,206,016 bits of memory are organized as 8,192 pages of 1,024 bytes (binary page size) or
1,056 bytes (standard DataFlash page size) each. In addition to the main memory, the
AT45DB642D also contains two SRAM buffers of 1,024 (binary buffer size) bytes/1,056 bytes
(standard DataFlash buffer size) each. The buffers allow receiving of data while a page in the
main Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM
emulation (bit or byte alterability) is easily handled with a self-contained three step read-modifywrite
operation. Unlike conventional Flash memories that are accessed randomly with multiple
address lines and a parallel interface, the DataFlash uses either a RapidS serial interface or a
8-bit Rapid8 interface to sequentially access its data. The simple sequential access dramatically
reduces active pin count, facilitates hardware layout, increases system reliability, minimizes
switching noise, and reduces package size. The device is optimized for use in many commercial
and industrial applications where high-density, low-pin count, low-voltage and low-power are
essential.
Memory Array
To provide optimal flexibility, the memory array of the AT45DB642D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates
the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page by page basis. The erase operations can
be performed at the chip, sector, block or page level.
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Table 15-1 on page 28 through Table 15-6 on
page 31. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit
opcode and the desired buffer or main memory address location. While the CS pin is low, toggling
the SCK/CLK pin controls the loading of the opcode and the desired buffer or main memory
address location through either the SI (serial input) pin or the 8-bit input pins (I/O7 - I/O0). All
instructions, addresses, and data are transferred with the most significant bit (MSB) first.
Buffer addressing for standard DataFlash page size (1056 bytes) is referenced in the datasheet
using the terminology BFA10 - BFA0 to denote the 11 address bits required to designate a byte
address within a buffer. Main memory addressing is referenced using the terminology PA12 -
PA0 and BA10 - BA0, where PA12 - PA0 denotes the 13 address bits required to designate a
page address and BA10 - BA0 denotes the 11 address bits required to designate a byte address
within the page.
For “Power of 2” binary page size (1024 bytes) the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA9 - BFA0 to denote the 10 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A22 - A0.
Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 8,192 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read from the standard DataFlash page size (1056 bytes), an
opcode of D2H must be clocked into the device followed by three address bytes (which comprise
the 24-bit page and byte address sequence) and a series of don’t care bytes (4 bytes if using the
serial interface or 19 bytes if using the 8-bit interface). The first 13 bits (PA12 - PA0) of the 24-bit
address sequence specify the page in main memory to be read, and the last 11 bits (BA10 -
BA0) of the 24-bit address sequence specify the starting byte address within that page. To start
a page read from the binary page size (1024 bytes), the opcode D2H must be clocked into the
device followed by three address bytes and a series of don’t care bytes (4 bytes if using the
serial interface or 19 bytes if using the 8-bit interface). The first 13 bits (A22 - A10) of the 24-bits
sequence specify which page of the main memory array to read, and the last 10 bits (A9 - A0) of
the 24-bits address sequence specify the starting byte address within the page. The don’t care
bytes that follow the address bytes are sent to initialize the read operation. Following the don’t
care bytes, additional pulses on SCK/CLK result in data being output on either the SO (serial
output) pin or the eight output pins (I/O7 - I/O0). The CS pin must remain low during the loading
of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of
a page in main memory is reached, the device will continue reading back at the beginning of the
same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pins (SO or I/O7 - I/O0). The maximum SCK/CLK frequency allowable for the Main
Memory Page Read is defined by the fSCK specification. The Main Memory Page Read bypasses
both data buffers and leaves the contents of the buffers unchanged.
[attachment=44665]
Description
The AT45DB642D is a 2.7-volt, dual-interface sequential access Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications. The
AT45DB642D supports RapidS serial interface and Rapid8 8-bit interface. RapidS serial interface
is SPI compatible for frequencies up to 66 MHz. The dual-interface allows a dedicated
serial interface to be connected to a DSP and a dedicated 8-bit interface to be connected to a
microcontroller or vice versa. However, the use of either interface is purely optional. Its
69,206,016 bits of memory are organized as 8,192 pages of 1,024 bytes (binary page size) or
1,056 bytes (standard DataFlash page size) each. In addition to the main memory, the
AT45DB642D also contains two SRAM buffers of 1,024 (binary buffer size) bytes/1,056 bytes
(standard DataFlash buffer size) each. The buffers allow receiving of data while a page in the
main Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM
emulation (bit or byte alterability) is easily handled with a self-contained three step read-modifywrite
operation. Unlike conventional Flash memories that are accessed randomly with multiple
address lines and a parallel interface, the DataFlash uses either a RapidS serial interface or a
8-bit Rapid8 interface to sequentially access its data. The simple sequential access dramatically
reduces active pin count, facilitates hardware layout, increases system reliability, minimizes
switching noise, and reduces package size. The device is optimized for use in many commercial
and industrial applications where high-density, low-pin count, low-voltage and low-power are
essential.
Memory Array
To provide optimal flexibility, the memory array of the AT45DB642D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates
the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page by page basis. The erase operations can
be performed at the chip, sector, block or page level.
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Table 15-1 on page 28 through Table 15-6 on
page 31. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit
opcode and the desired buffer or main memory address location. While the CS pin is low, toggling
the SCK/CLK pin controls the loading of the opcode and the desired buffer or main memory
address location through either the SI (serial input) pin or the 8-bit input pins (I/O7 - I/O0). All
instructions, addresses, and data are transferred with the most significant bit (MSB) first.
Buffer addressing for standard DataFlash page size (1056 bytes) is referenced in the datasheet
using the terminology BFA10 - BFA0 to denote the 11 address bits required to designate a byte
address within a buffer. Main memory addressing is referenced using the terminology PA12 -
PA0 and BA10 - BA0, where PA12 - PA0 denotes the 13 address bits required to designate a
page address and BA10 - BA0 denotes the 11 address bits required to designate a byte address
within the page.
For “Power of 2” binary page size (1024 bytes) the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA9 - BFA0 to denote the 10 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A22 - A0.
Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 8,192 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read from the standard DataFlash page size (1056 bytes), an
opcode of D2H must be clocked into the device followed by three address bytes (which comprise
the 24-bit page and byte address sequence) and a series of don’t care bytes (4 bytes if using the
serial interface or 19 bytes if using the 8-bit interface). The first 13 bits (PA12 - PA0) of the 24-bit
address sequence specify the page in main memory to be read, and the last 11 bits (BA10 -
BA0) of the 24-bit address sequence specify the starting byte address within that page. To start
a page read from the binary page size (1024 bytes), the opcode D2H must be clocked into the
device followed by three address bytes and a series of don’t care bytes (4 bytes if using the
serial interface or 19 bytes if using the 8-bit interface). The first 13 bits (A22 - A10) of the 24-bits
sequence specify which page of the main memory array to read, and the last 10 bits (A9 - A0) of
the 24-bits address sequence specify the starting byte address within the page. The don’t care
bytes that follow the address bytes are sent to initialize the read operation. Following the don’t
care bytes, additional pulses on SCK/CLK result in data being output on either the SO (serial
output) pin or the eight output pins (I/O7 - I/O0). The CS pin must remain low during the loading
of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of
a page in main memory is reached, the device will continue reading back at the beginning of the
same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pins (SO or I/O7 - I/O0). The maximum SCK/CLK frequency allowable for the Main
Memory Page Read is defined by the fSCK specification. The Main Memory Page Read bypasses
both data buffers and leaves the contents of the buffers unchanged.