21-12-2012, 06:33 PM
ARM PROCESSOR
[attachment=44853]
HISTORY OF ARM PROCESSOR
From 1985 to 1990 ARM was known as Acorn RISC Machine
Developed the first Processor (Acorn RISC Machine) in1985 at Acorn Computers Limited
In 1990 established a new company named Advanced RISC Machine Limited with the development of ARM6
ARM: Advanced RISC Machine Limited
CLASSIFICATION OF PROCESSOR ARCHITECTURE
There are two types of Processor Architecture based on the instruction set
CISC : Complex Instruction Set Computing
RISC : Reduced Instruction Set Computing
FEATURES OF ARM PROCESSOR
Incorporate features of RISC design
-a large register file
-a load/store architecture
-uniform and fixed length instruction field
-simple addressing mode
•Other ARM architecture features
-Arithmetic Logic Unit and barrel shifter
-auto increment and decrement addressing mode
-conditional execution of instructions
BARREL SHIFTER
Rm operand passes through a barrel shifter hardware block before it enters the ALU.
possible to execute both an arithmetic operation and a shift operation in one instruction.
The barrel shifter can shift the 32-bit Rm operand any number of bit positions (up to 32 bits, left or right) before entering the ALU.
The bit shift is entirely an asynchronous operation, so no additional clock cycles are required to facilitate the shift operation
OPERAND SIZE
The ARM architecture permits operations on:
Bytes : 8 bits
Half -Words : 16 bits
Words : 32 bits
The ARM architecture supports both big endian and little endian data packing through the proper configuration of the core.
The architecture does default to little endian as the native mode.
[attachment=44853]
HISTORY OF ARM PROCESSOR
From 1985 to 1990 ARM was known as Acorn RISC Machine
Developed the first Processor (Acorn RISC Machine) in1985 at Acorn Computers Limited
In 1990 established a new company named Advanced RISC Machine Limited with the development of ARM6
ARM: Advanced RISC Machine Limited
CLASSIFICATION OF PROCESSOR ARCHITECTURE
There are two types of Processor Architecture based on the instruction set
CISC : Complex Instruction Set Computing
RISC : Reduced Instruction Set Computing
FEATURES OF ARM PROCESSOR
Incorporate features of RISC design
-a large register file
-a load/store architecture
-uniform and fixed length instruction field
-simple addressing mode
•Other ARM architecture features
-Arithmetic Logic Unit and barrel shifter
-auto increment and decrement addressing mode
-conditional execution of instructions
BARREL SHIFTER
Rm operand passes through a barrel shifter hardware block before it enters the ALU.
possible to execute both an arithmetic operation and a shift operation in one instruction.
The barrel shifter can shift the 32-bit Rm operand any number of bit positions (up to 32 bits, left or right) before entering the ALU.
The bit shift is entirely an asynchronous operation, so no additional clock cycles are required to facilitate the shift operation
OPERAND SIZE
The ARM architecture permits operations on:
Bytes : 8 bits
Half -Words : 16 bits
Words : 32 bits
The ARM architecture supports both big endian and little endian data packing through the proper configuration of the core.
The architecture does default to little endian as the native mode.