21-12-2012, 06:42 PM
DIRECT MEMORY ACCESS
[attachment=44863]
Introduction
An important aspect governing the Computer System performance is the transfer of data between memory and I/O devices.
The operation involves loading programs or data files from disk into memory, saving file on disk, and accessing virtual memory pages on any secondary storage medium.
Computer System with DMA
Consider a typical system consisting of a CPU ,memory and one or more input/output devices as shown in fig. Assume one of the I/O devices is a disk drive and that the computer must load a program from this drive into memory.
The CPU would read the first byte of the program and then write that byte to memory. Then it would do the same for the second byte, until it had loaded the entire program into memory.
Implementing DMA in a Computer System
A DMA controller implements direct memory access in a computer system.
It connects directly to the I/O device at one end and to the system buses at the other end. It also interacts with the CPU, both via the system buses and two new direct connections.
It is sometimes referred to as a channel. In an alternate configuration, the DMA controller may be incorporated directly into the I/O device.
Data Transfer using DMA Controller
To transfer data from an I/O device to memory, the DMA controller first sends a Bus Request to the CPU by setting BR to 1. When it is ready to grant this request, the CPU sets it’s Bus grant signal, BG to 1.
The CPU also tri-states it’s address,data, and control lines thus truly granting control of the system buses to the DMA controller.
The CPU will continue to tri-state it’s outputs as long as BR is asserted.
Internal Configuration
The DMA controller includes several registers :-
The DMA Address Register contains the memory address to be used in the data transfer. The CPU treats this signal as one or more output ports.
The DMA Count Register, also called Word Count Register, contains the no. of bytes of data to be transferred. Like the DMA address register, it too is treated as an O/P port (with a diff. Address) by the CPU.
The DMA Control Register accepts commands from the CPU. It is also treated as an O/P port by the CPU.
[attachment=44863]
Introduction
An important aspect governing the Computer System performance is the transfer of data between memory and I/O devices.
The operation involves loading programs or data files from disk into memory, saving file on disk, and accessing virtual memory pages on any secondary storage medium.
Computer System with DMA
Consider a typical system consisting of a CPU ,memory and one or more input/output devices as shown in fig. Assume one of the I/O devices is a disk drive and that the computer must load a program from this drive into memory.
The CPU would read the first byte of the program and then write that byte to memory. Then it would do the same for the second byte, until it had loaded the entire program into memory.
Implementing DMA in a Computer System
A DMA controller implements direct memory access in a computer system.
It connects directly to the I/O device at one end and to the system buses at the other end. It also interacts with the CPU, both via the system buses and two new direct connections.
It is sometimes referred to as a channel. In an alternate configuration, the DMA controller may be incorporated directly into the I/O device.
Data Transfer using DMA Controller
To transfer data from an I/O device to memory, the DMA controller first sends a Bus Request to the CPU by setting BR to 1. When it is ready to grant this request, the CPU sets it’s Bus grant signal, BG to 1.
The CPU also tri-states it’s address,data, and control lines thus truly granting control of the system buses to the DMA controller.
The CPU will continue to tri-state it’s outputs as long as BR is asserted.
Internal Configuration
The DMA controller includes several registers :-
The DMA Address Register contains the memory address to be used in the data transfer. The CPU treats this signal as one or more output ports.
The DMA Count Register, also called Word Count Register, contains the no. of bytes of data to be transferred. Like the DMA address register, it too is treated as an O/P port (with a diff. Address) by the CPU.
The DMA Control Register accepts commands from the CPU. It is also treated as an O/P port by the CPU.