21-12-2012, 06:56 PM
CASE STUDY OF PENTIUM PRO PROCESSOR
[attachment=44868]
INTRODUCTION
The Pentium Pro processor, is an X86 micro processor introduced by Intel in 1995.
It is a 32-bit microprocessor.
It is based upon a superscalar micro-architecture.
Main goal in the design of the micro-architecture was to exceed the Pentium processor performance .
About 5.5 million transistors are incorporated in it.
FEATURES
It is a superscalar CISC processor with a RISC core.
Pentium Pro processor microarchitecture is a three-way superscalar, pipelined architecture.
The Pentium Pro processor uses a 12 stage superpipeline .
Supports out-of-order execution mechanism called dynamic execution.
It has a wider 36-bit address bus which can access up to 64GB of memory.
First stage includes
Instructions are fetched from I-cache and sent to the I-buffer.
Up to 3 CISC instructions are decoded and converted to RISC instructions in each cycle.
Conversion is done by means of
Two simple decoders(D1 & D2)
Accepts single instruction and convert it to single µop.
General decoder(D3)
Instructions resulting in maximum four µops are handled.
Microinstruction sequencer(MIS)
Instructions resulting in more than four µops are handled.
Operand fetching
done during instruction issue.
renamed register numbers are passed to both architectural register file and ROB
issue of µops in to CRS
A value or tag is forwarded to CRS.
If valid entry for renamed register number is found in ROB then take the operand value.
If no valid entry ,a tag will be passed to CRS.
[attachment=44868]
INTRODUCTION
The Pentium Pro processor, is an X86 micro processor introduced by Intel in 1995.
It is a 32-bit microprocessor.
It is based upon a superscalar micro-architecture.
Main goal in the design of the micro-architecture was to exceed the Pentium processor performance .
About 5.5 million transistors are incorporated in it.
FEATURES
It is a superscalar CISC processor with a RISC core.
Pentium Pro processor microarchitecture is a three-way superscalar, pipelined architecture.
The Pentium Pro processor uses a 12 stage superpipeline .
Supports out-of-order execution mechanism called dynamic execution.
It has a wider 36-bit address bus which can access up to 64GB of memory.
First stage includes
Instructions are fetched from I-cache and sent to the I-buffer.
Up to 3 CISC instructions are decoded and converted to RISC instructions in each cycle.
Conversion is done by means of
Two simple decoders(D1 & D2)
Accepts single instruction and convert it to single µop.
General decoder(D3)
Instructions resulting in maximum four µops are handled.
Microinstruction sequencer(MIS)
Instructions resulting in more than four µops are handled.
Operand fetching
done during instruction issue.
renamed register numbers are passed to both architectural register file and ROB
issue of µops in to CRS
A value or tag is forwarded to CRS.
If valid entry for renamed register number is found in ROB then take the operand value.
If no valid entry ,a tag will be passed to CRS.